公开(公告)号：US4821084A

公开(公告)日：1989-04-11

申请号：US5668

申请日：1987-01-21

申请人： Masanori Kinugasa ,  Fuminari Tanaka ,  Hiroshi Shigehara ,  Hirokata Ohta

发明人： Masanori Kinugasa ,  Fuminari Tanaka ,  Hiroshi Shigehara ,  Hirokata Ohta

IPC分类号： H01L29/78 ,  H01L23/528 ,  H01L27/118 ,  H01L29/417 ,  H01L29/423 ,  H01L29/94 ,  H01L27/10

CPC分类号： H01L23/528 ,  H01L27/11898 ,  H01L29/41758 ,  H01L2924/0002

摘要： Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.

摘要翻译： 源极电极层和漏电极的延伸方向平行于交替排列的源极区域和漏极区域的阵列的行或列，从而形成比常规晶体管宽的源极和漏极电极层的宽度以获得大的互导 。

公开(公告)号：US4264968A

公开(公告)日：1981-04-28

申请号：US864714

申请日：1977-12-27

申请人： Yasoji Suzuki ,  Fuminari Tanaka ,  Yasushi Sato

发明人： Yasoji Suzuki ,  Fuminari Tanaka ,  Yasushi Sato

IPC分类号： G01R19/00 ,  G04G3/02 ,  G04G9/00 ,  G04G99/00 ,  G04C3/00

CPC分类号： G04G99/00 ,  G04G3/022

摘要： There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.

摘要翻译： 提供了一种电子钟表基本电路，包括用于产生1Hz脉冲的脉冲发生电路，具有包括连接到脉冲发生电路的输出端的端子的多个端子的第一端子组，具有端子的第二端子组 分别连接到第一终端组的终端，与第二终端组耦合的10个比例计数器，连接到10个比例计数器的6个比例计数器，显示单元和与10个比例计数器耦合的解码器，6 缩放计数器并解码10和6比例计数器的内容，并将解码的内容传送到显示单元。 第一和第二端子组彼此适当地联接。 10个刻度计数器和6个刻度计数器的组合被适当修改，以便根据需要形成12个，24个或60个刻度计数器。

公开(公告)号：US5034629A

公开(公告)日：1991-07-23

申请号：US552855

申请日：1990-07-16

申请人： Masanori Kinugasa ,  Fuminari Tanaka ,  Satoshi Nonaka ,  Munenobu Kida

发明人： Masanori Kinugasa ,  Fuminari Tanaka ,  Satoshi Nonaka ,  Munenobu Kida

IPC分类号： H03K17/16 ,  G11C11/409 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/00361 ,  H03K19/09429 ,  H03K19/0948

摘要： In an output circuit for use in a semiconductor IC comprising a CMOS transistors constituting an output buffer, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element. The transfer gate reduces the changes in the gate potentials of output transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output transistors, is minimized.

公开(公告)号：US4924339A

公开(公告)日：1990-05-08

申请号：US291476

申请日：1988-12-28

申请人： Shigeru Atsumi ,  Toru Yoshida ,  Yasuo Kawahara ,  Fuminari Tanaka

发明人： Shigeru Atsumi ,  Toru Yoshida ,  Yasuo Kawahara ,  Fuminari Tanaka

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H02H9/04

CPC分类号： H01L27/0251

摘要： A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.

公开(公告)号：US4618847A

公开(公告)日：1986-10-21

申请号：US586721

申请日：1984-03-06

申请人： Tetsuya Iida ,  Fuminari Tanaka

发明人： Tetsuya Iida ,  Fuminari Tanaka

IPC分类号： H03M1/68 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03M1/687

摘要： A C-R type D/A converter which comprises a C-array type D/A converter used to convert the upper bit data of a digital input data on a digital-to-analog basis, an R type D/A converter used to convert the lower bit data of the digital input data, and a coupling capacitor connected between an output terminal of the C-array type D/A converter and an output terminal of the R type D/A converter.

摘要翻译： 一种CR型D / A转换器，其包括用于以数字模拟为基础转换数字输入数据的高位数据的C阵列型D / A转换器，用于转换数字输入数据的R型D / A转换器 数字输入数据的低位数据和连接在C阵列型D / A转换器的输出端和R型D / A转换器的输出端之间的耦合电容器。

公开(公告)号：US4532612A

公开(公告)日：1985-07-30

申请号：US450049

申请日：1982-12-15

申请人： Fuminari Tanaka ,  Yoshihiro Iwamoto

发明人： Fuminari Tanaka ,  Yoshihiro Iwamoto

IPC分类号： G11C17/00 ,  G11C17/08 ,  G11C17/12 ,  G11C17/14 ,  G11C11/40

CPC分类号： G11C17/14 ,  G11C17/08

摘要： A dynamic read only memory comprises a plurality of ROM blocks and a control circuit composed of a plurality of MOSFETs respectively connected to the column lines. The control circuit keeps the data from the ROM block not containing a specified memory cell at a discharged level.

摘要翻译： 动态只读存储器包括多个ROM块和由分别连接到列线的多个MOSFET组成的控制电路。 控制电路将来自不包含指定存储单元的ROM块的数据保持在放电电平。

公开(公告)号：US5128567A

公开(公告)日：1992-07-07

申请号：US345259

申请日：1989-05-01

申请人： Fuminari Tanaka ,  Satoshi Nonaka

发明人： Fuminari Tanaka ,  Satoshi Nonaka

IPC分类号： H01L29/43 ,  H03K17/00 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H01L29/435 ,  H03K17/164 ,  H03K19/00361 ,  H03K2217/0036

摘要： An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.

公开(公告)号：US4701877A

公开(公告)日：1987-10-20

申请号：US675303

申请日：1984-11-27

申请人： Masayuki Sahoda ,  Fuminari Tanaka ,  Tetsuya Iida

发明人： Masayuki Sahoda ,  Fuminari Tanaka ,  Tetsuya Iida

IPC分类号： G06F7/505 ,  G06F7/50 ,  G06F7/502 ,  G06F7/506

CPC分类号： G06F7/502 ,  G06F2207/3876

摘要： In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.

摘要翻译： 在并行加法器电路中，交替地连接第一和第二全加法器，每个加法器具有加数输入端，加法输入端，和输出端，进位输入端和进位输出端，使得前面的进位输出端 全加器直接连接到后续全加器的进位输入端。 为了缩短进位传播延迟时间，第一全加器被布置为从前一级接收反向进位信号（FALSE），并且向后级提供进位信号（TRUE），而第二全加器布置 从前级接收进位信号（TRUE），并向后级提供反转进位信号（FALSE）。

公开(公告)号：US4404663A

公开(公告)日：1983-09-13

申请号：US234438

申请日：1981-02-13

申请人： Yukihiro Saeki ,  Fuminari Tanaka ,  Yasoji Suzuki

发明人： Yukihiro Saeki ,  Fuminari Tanaka ,  Yasoji Suzuki

IPC分类号： G06F1/18 ,  G06F3/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C5/063 ,  G11C7/10 ,  G11C7/1006

摘要： An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.

摘要翻译： 一种集成电路，其中门电路设置在安装在半导体衬底上的总线上。 门电路用于将未使用的电路块与通过用于高速数据传输的输入 - 输出电路连接到总线的其它电路块分离，从而减少可能通过分离的总线赋予总线的寄生电容 电路块。 输入输出电路由时钟反相器构成。 门电路由CxMOS传输门形成。 输入输出电路和门电路如此连接，使逆变器的门打开，则CxMOS传输门关闭; 并且逆变器的门关闭​​，则CxMOS传输门打开。

公开(公告)号：US4890016A

公开(公告)日：1989-12-26

申请号：US197979

申请日：1988-05-24

申请人： Fuminari Tanaka ,  Satoshi Nonaka

发明人： Fuminari Tanaka ,  Satoshi Nonaka

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00361 ,  H03K19/00392

摘要： An output circuit includes a plurality of output buffer circuits and a plurality of pre-buffer circuits connected to drive the output buffer circuits. Some of the pre-buffer circuits are each constituted by P- and N-channel MOS transistors having channel widths or channel lengths which are large enough to drive the output buffer circuits, and the remaining pre-buffer circuits are each constituted by P- and N-channel MOS transistors whose channel widths and channel lengths are so determined as to set the current driving ability thereof sufficiently smaller than that of the corresponding output buffer circuits.

摘要翻译： 输出电路包括多个输出缓冲电路和连接以驱动输出缓冲电路的多个预缓冲器电路。 一些预缓冲电路各自由具有足够大的驱动输出缓冲电路的沟道宽度或沟道长度的P-沟道MOS晶体管和N沟道MOS晶体管构成，其余的预缓冲电路各自由P-和 其通道宽度和沟道长度被确定为将其电流驱动能力设定得足够小于对应的输出缓冲电路的电流驱动能力的N沟道MOS晶体管。