公开(公告)号：US4255678A

公开(公告)日：1981-03-10

申请号：US962221

申请日：1978-11-20

申请人： Yasoji Suzuki ,  Kiyofumi Ochii ,  Hirozi Asahi

发明人： Yasoji Suzuki ,  Kiyofumi Ochii ,  Hirozi Asahi

IPC分类号： G11C11/41 ,  G11C11/409 ,  G11C11/419 ,  H03K5/24 ,  G11C7/00

CPC分类号： G11C11/419

摘要： A voltage sense circuit in which first and second parallel connections of complementary MOS transistors are connected between a pair of signal lines connected to memory cells and outputs of a flip-flop circuit for detecting a potential change of the signal line caused by data readout from an accessed memory cell. MOS transistors of one channel type in the parallel connections are adapted to precharge output node capacitors of the flip-flop circuit to a supply voltage level, while MOS transistors of the other channel type are adapted to couple complementary output voltage levels of the flip-flop circuit produced after the data readout and operation of the flip-flop circuit to the signal lines. Use of the parallel connections of complementary MOS transistors enables the application of a single power source for producing gate signals of these MOS transistors.

摘要翻译： 一种电压检测电路，其中互补MOS晶体管的第一和第二并联连接在连接到存储单元的一对信号线之间，并且用于检测由数据读出引起的信号线的电位变化的触发器电路的输出 存取存储单元 并联连接中的一个通道类型的MOS晶体管适于将触发器电路的输出节点电容器预充电到电源电压电平，而另一个通道类型的MOS晶体管适于耦合触发器的互补输出电压电平 在触发电路的数据读出和操作到信号线之后产生的电路。 使用互补MOS晶体管的并联连接使得能够应用单个电源来产生这些MOS晶体管的栅极信号。

公开(公告)号：US4233672A

公开(公告)日：1980-11-11

申请号：US962222

申请日：1978-11-20

申请人： Yasoji Suzuki ,  Kiyofumi Ochii ,  Hirozi Asahi

发明人： Yasoji Suzuki ,  Kiyofumi Ochii ,  Hirozi Asahi

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/02 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78 ,  G11C7/00

CPC分类号： H01L27/0222 ,  G11C11/412 ,  H01L27/0927 ,  H01L27/0218 ,  H01L27/105

摘要： A CMOS semiconductor memory device in which a memory cell array and peripheral circuits are formed on the same semiconductor substrate. Wells of the peripheral circuits with MOS transistors of one channel type formed therein are supplied with a PN junction reverse bias potential higher than that for wells of the memory cell array during the memory operation, while the potential at the peripheral circuit wells is made equal to the potential at the wells of the memory cell array when the memory is not operating. High-speed operation of the memory device may be achieved because the junction capacitance of the MOS transistors formed in the peripheral circuit wells is reduced when the memory is operating.

摘要翻译： 一种其中存储单元阵列和外围电路形成在同一半导体衬底上的CMOS半导体存储器件。 在存储器操作期间，其中形成有一个沟道类型的MOS晶体管的外围电路的阱被提供有比在存储器操作期间高于存储器单元阵列的阱的PN结反向偏压电位，而外围电路阱的电位等于 当存储器不工作时，存储单元阵列的阱处的电位。 可以实现存储器件的高速操作，因为当存储器工作时，外围电路阱中形成的MOS晶体管的结电容减小。

公开(公告)号：US4136292A

公开(公告)日：1979-01-23

申请号：US827721

申请日：1977-08-25

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/412 ,  G11C11/419 ,  H03K5/02 ,  H03K5/20

CPC分类号： G11C11/419 ,  G11C11/4091 ,  H03K5/023

摘要： A voltage sensing circuit of differential input type includes at least one differential amplifier circuit connected between two complementary data lines of a semiconductor memory. The differential amplifier circuit detects data in response to a minute potential difference between the data lines and amplifies the same by a substantial change in conductance g.sub.m of metal oxide semiconductor field effect transistors (MOSFET) used in the circuit. When data is read from a semiconductor memory onto the data lines, the differential amplifier sensing circuit detects the data quickly by detecting potential changes of the data lines.

公开(公告)号：US4044342A

公开(公告)日：1977-08-23

申请号：US679177

申请日：1976-04-22

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/405 ,  G11C11/406 ,  G11C11/40

CPC分类号： G11C11/406 ,  G11C11/405

摘要： The dynamic type semiconductor memory device comprises a refresh circuit and a plurality of memory cells which are connected between a data input line and a data output line, a plurality of read/write command signal lines and a plurality of word selection lines provided for respective semiconductor memory cells. Each semiconductor memory cell comprises serially connected first p-channel MOS transistor and a second n-channel MOS transistor having gate electrodes connected to the read/write command signal line and the data input line respectively, a third p-channel MOS transistor connected between the data output line and the word selection line and having a gate electrode connected to the node between the first and second transistors, and a parasitic capacitance connected to the node between the first and second transistors for storing data.

摘要翻译： 动态型半导体存储器件包括一个连接在数据输入线和数据输出线之间的刷新电路和多个存储器单元，多个读/写命令信号线和为各个半导体提供的多个字选择线 记忆细胞 每个半导体存储单元包括串联连接的第一p沟道MOS晶体管和第二n沟道MOS晶体管，第二n沟道MOS晶体管分别具有连接到读取/写入命令信号线和数据输入线的栅电极，第三p沟道MOS晶体管连接在 数据输出线和字选择线，并且具有连接到第一和第二晶体管之间的节点的栅电极，以及连接到用于存储数据的第一和第二晶体管之间的节点的寄生电容。

公开(公告)号：US4151610A

公开(公告)日：1979-04-24

申请号：US777664

申请日：1977-03-15

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/404 ,  G11C11/406 ,  H01L27/108 ,  G11C11/24 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/404 ,  G11C11/406 ,  H01L27/10805

摘要： A semiconductor memory device comprising an N conductivity type semiconductor substrate, a P conductivity type well formed in a specified section of the surface of the semiconductor substrate, N conductivity type source and drain regions formed in the P conductivity type well, and a gate insulation layer deposited on the surface of the well over the source and drain regions. The P conductivity type well has a higher impurity concentration than the N conductivity type semiconductor substrate and the N conductivity type source and drain regions have a higher impurity concentration than the P conductivity type well. An insulation film is formed on the drain region and the insulation film, a metal electrode layer deposited on the insulation film and drain region collectively institute a capacitor.

摘要翻译： 一种半导体存储器件，包括N导电型半导体衬底，在半导体衬底的表面的特定部分中良好地形成的P导电型，在P导电型阱中形成的N导电型源极和漏极区域以及栅极绝缘层 沉积在源极和漏极区上的阱的表面上。 P导电类型的阱具有比N导电型半导体衬底更高的杂质浓度，并且N导电型源区和漏区具有比P导电类型井更高的杂质浓度。 在漏极区域和绝缘膜上形成绝缘膜，沉积在绝缘膜和漏极区域上的金属电极层共同构成电容器。

公开(公告)号：US4103345A

公开(公告)日：1978-07-25

申请号：US680236

申请日：1976-04-26

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/06

CPC分类号： G11C11/412 ,  G11C11/419

摘要： Provided is a semiconductor memory device comprising a pair of data input lines, a pair of data output lines, memory cells arranged in the form of a matrix, the memory cell of each column being connected between a pair of data lines, the memory cell of each row being connected to a row selection line, a memory cell selection circuit for generating column and row designation signals in order to select a desired one of said memory cells, a switching circuit disposed in each column and turned on upon receipt of a column designation signal from the memory cell selection circuit to connect the data line to a corresponding one of the data input lines, and a data detection circuit connected between the pair of data lines of each column and adapted, upon receipt of a column signal from the memory cell selection circuit, to transmit an inverted signal of a signal on the data line onto the data output line.

公开(公告)号：US4114192A

公开(公告)日：1978-09-12

申请号：US777663

申请日：1977-03-15

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/412 ,  G11C11/419 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H03K3/356 ,  H03K19/096 ,  G11C7/06

CPC分类号： H03K19/0963 ,  G11C11/412 ,  G11C11/419 ,  H03K3/356

摘要： A semiconductor memory device includes a memory circuit formed of a plurality of matrix-arranged memory cells, a plurality of output data lines, each of which is connected to memory cells arranged in the same column of the matrix memory circuit, and a plurality of data-sensing circuits for delivering output data from the matrix memory circuit to an output device. The data-sensing circuits are divided into a plurality of groups, and the semiconductor memory device further comprises clocked inverters whose input terminals are connected to the output terminals of the respective groups of sensing circuits and whose output terminals are connected to the output device, and a control circuit which, when one of the data-sensing circuits issues an output, supplies an energizing signal to that of the clocked inverters which is connected to said one data-sensing circuit.

公开(公告)号：US5563434A

公开(公告)日：1996-10-08

申请号：US468385

申请日：1995-06-06

申请人： Kiyofumi Ochii

发明人： Kiyofumi Ochii

IPC分类号： G11C11/404 ,  G11C11/4074 ,  H01L27/108 ,  H01L29/92 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C11/404 ,  G11C11/4074 ,  H01L27/108

摘要： The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.

摘要翻译： 选择晶体管的栅极连接到字线，其源极连接到位线。 选择晶体管的漏极连接到构成薄膜晶体管结构的电容器的存储节点。 电容器具有与存储节点绝缘的平板电极，与存储节点相对设置的板电极的部分形成为具有低于其余部分的杂质浓度，并且反相层形成在相应部分中 根据存储在存储节点中的数据。 平板电极连接到脉冲产生装置，在数据读出操作中从脉冲发生装置输出脉冲信号，并且通过脉冲信号使平板电极的电位升高。

公开(公告)号：US5282162A

公开(公告)日：1994-01-25

申请号：US704923

申请日：1991-05-23

申请人： Kiyofumi Ochii

发明人： Kiyofumi Ochii

IPC分类号： G11C11/405 ,  H01L27/108 ,  G11C11/40

CPC分类号： H01L27/108 ,  G11C11/405

摘要： The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on. Therefore, a current can be supplied to the bit line BL from the pulse generation circuit 11 via the transistor Q3 and the selected transistor Q1.

摘要翻译： 用作选择晶体管的晶体管Q1的栅极连接到字线，其源极连接到位线BL。 用作单元电容器的晶体管Q2的栅极连接到晶体管Q1的漏极，其漏极连接到脉冲发生电路。 根据存储的数据确定在晶体管Q2的沟道区域中是否形成反相层。 在具有作为存储数据存储的数据“1”的晶体管Q2的沟道区域中形成反相层。 晶体管Q2的源极连接到晶体管Q3的栅极。 晶体管Q3的漏极连接到脉冲发生电路11，其源极连接到晶体管Q1的漏极。 当在存储的数据读取操作中从脉冲发生电路11提供预置电压时，形成有反相层的晶体管Q2导通，在这种情况下，晶体管Q3导通。 因此，可以经由晶体管Q3和所选择的晶体管Q1从脉冲发生电路11向位线BL提供电流。

公开(公告)号：US5132929A

公开(公告)日：1992-07-21

申请号：US288183

申请日：1988-12-22

申请人： Kiyofumi Ochii

发明人： Kiyofumi Ochii

IPC分类号： H01L27/10 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00 ,  G11C29/04 ,  G11C29/50 ,  H01L21/66

CPC分类号： G11C11/412 ,  G11C11/419 ,  G11C29/50 ,  G11C11/41 ,  G11C2029/5006 ,  H01L2924/0002

摘要： A static random access memory has a plurality of memory cells. Each memory cell is made up of two high-resistance resistors functioning as load elements, and a flip-flop circuit. The flip-flop circuit is made up of two inverters including MOS transistors which are formed in a substrate and used as drive elements. The sources of the two MOS transistors are coupled to each other and electrically isolated from the substrate. Another MOS transistor is connected between the common source of the flip-flop MOS transistors and the source of a power-supply voltage. A MOS transistor is coupled between the common source of the MOS transistors and the source of a ground voltage. A plurality of bit lines supplies data to, and receives data from, the memory cells. A resistance element is connected between each bit line and the source of the power-supply voltage, and an output terminal outputs the voltage at one end of this resistance element. Two different voltages are applied to the sources of the two MOS transistors. One voltage is applied during normal operation of the memory and the other voltage is applied during leakage current detection testing.

摘要翻译： 静态随机存取存储器具有多个存储单元。 每个存储单元由用作负载元件的两个高电阻电阻器和触发器电路组成。 触发器电路由两个反相器组成，包括形成在衬底中并用作驱动元件的MOS晶体管。 两个MOS晶体管的源极彼此耦合并与衬底电隔离。 另一MOS晶体管连接在触发器MOS晶体管的公共源和电源电压源之间。 MOS晶体管耦合在MOS晶体管的公共源和接地电压源之间。 多个位线向存储器单元提供数据并从存储单元接收数据。 电阻元件连接在每个位线和电源电压源之间，输出端输出该电阻元件一端的电压。 两个不同的电压施加到两个MOS晶体管的源极。 在存储器的正常运行期间施加一个电压，并且在泄漏电流检测测试期间施加另一个电压。