公开(公告)号：US07474876B2

公开(公告)日：2009-01-06

申请号：US10916776

申请日：2004-08-12

申请人： Jörg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

发明人： Jörg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

IPC分类号： H04B17/00 ,  H03C1/62

CPC分类号： H04L27/368

摘要： A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24). Moreover, the invention provides attenuating means (50) for attenuation of the signal dependent on the characteristics of the telecommunication channel.

摘要翻译： 用于生产标准兼容信号（例如电信网络中的脉冲型信号）的装置用于以特定信号形式产生和适应和/或预失真信号，该特定信号形式取决于指定的标准信号形式 在一个标准。 该装置包括用于产生具有特定信号形式的信号的信号产生装置（10）和用于信号的自适应或预失真的信号调节装置（20）。 根据本发明的信号产生装置（10）通过使用可编程移位寄存器（14）进行数字实现，该可编程移位寄存器（14）包含用于与数字输入信号（1）相乘的标准信号形式指定的乘法器。 信号调节装置（20）包括数字滤波器（22）与下游多路复用器（24）的串行连接形式的基本上可伸缩的数字滤波器装置。 此外，本发明提供衰减装置（50），用于根据电信信道的特性衰减信号。

公开(公告)号：US20050090203A1

公开(公告)日：2005-04-28

申请号：US10916776

申请日：2004-08-12

申请人： Jorg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

发明人： Jorg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

IPC分类号： H03C1/62 ,  H04B1/10 ,  H04B17/00 ,  H04L25/08 ,  H04L27/36 ,  H04L29/08

CPC分类号： H04L27/368

摘要： A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24). Moreover, the invention provides attenuating means (50) for attenuation of the signal dependent on the characteristics of the telecommunication channel.

摘要翻译： 用于生产标准兼容信号（例如电信网络中的脉冲型信号）的装置用于以特定信号形式产生和适应和/或预失真信号，该特定信号形式取决于指定的标准信号形式 在一个标准。 该装置包括用于产生具有特定信号形式的信号的信号产生装置（10）和用于信号的自适应或预失真的信号调节装置（20）。 根据本发明的信号产生装置（10）通过使用可编程移位寄存器（14）进行数字实现，该可编程移位寄存器（14）包含用于与数字输入信号（1）相乘的标准信号形式指定的乘法器。 信号调节装置（20）包括数字滤波器（22）与下游多路复用器（24）的串行连接形式的基本上可伸缩的数字滤波器装置。 此外，本发明提供衰减装置（50），用于根据电信信道的特性衰减信号。

公开(公告)号：US07095803B2

公开(公告)日：2006-08-22

申请号：US10225637

申请日：2002-08-22

申请人： Lajos Gazsi ,  Peter Gregorius

发明人： Lajos Gazsi ,  Peter Gregorius

IPC分类号： H04L27/22

CPC分类号： H04L25/08 ,  H03M1/185 ,  H04B3/145

摘要： To reconstruct data transmitted over a transmission path, for example a cable, the corresponding signal received by the receiver is firstly amplified and subsequently made discrete by means of an A/D-converter (6), in order to obtain a suitable digital signal, whereby the signal amplified for this purpose is scanned with a relatively low sampling rate, which can frequently lie in the Nyquist range or can be even less than the Nyquist frequency. Subsequently the signal made discrete in this way is filtered by means of a digital high pass filter (8) and equalized by means of a digital cable approximation filter (9) to compensate any distortion occurring during the transmission over the transmission path. By means of a phase locked loop (14, 18) a regenerated clock (CLK) and synchronous with this clock the originally transmitted data (DATA) is recovered from the digital signal processed in this way.

摘要翻译： 为了重建通过传输路径（例如电缆）传输的数据，接收机接收的相应信号首先被放大并随后通过A / D转换器（6）离散，以获得合适的数字信号， 由此为了这个目的而放大的信号以相对较低的采样速率被扫描，其可以频繁地位于奈奎斯特（Nyquist）范围内，或者甚至可以小于奈奎斯特（Nyquist）频率。 随后，以这种方式离散的信号通过数字高通滤波器（8）进行滤波，并通过数字电缆近似滤波器（9）进行均衡，以补偿在传输路径上传输期间发生的任何失真。 通过锁相环（14,18）再生时钟（CLK）并与该时钟同步，原始传输的数据（DATA）从以这种方式处理的数字信号中恢复。

公开(公告)号：US07349508B2

公开(公告)日：2008-03-25

申请号：US10714202

申请日：2003-11-14

申请人： Thomas Duda ,  Lajos Gaszi ,  Peter Gregorius ,  Torsten Hinz ,  Martin Renner

发明人： Thomas Duda ,  Lajos Gaszi ,  Peter Gregorius ,  Torsten Hinz ,  Martin Renner

IPC分类号： H04L7/00

CPC分类号： H04L25/03885

摘要： A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method includes amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter; performing a cable approximation by means of a digitally implemented cable approximation filter in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop.

摘要翻译： 公开了一种用于通过传输链路传输已被失真的信号重建以符号速率计时的数据的方法和装置。 该方法或分别主要通过数字电路技术执行或实现的装置，以便提高数据恢复的质量。 该方法包括放大由传输衰减的信号幅度; 过滤高于符号率的高频干扰频率; 通过模拟/数字转换器离散模拟信号; 通过数字实现的电缆近似滤波器执行电缆近似，以获得均衡的信号; 并通过锁相环从均衡信号中恢复数据。

公开(公告)号：US08305834B2

公开(公告)日：2012-11-06

申请号：US12710800

申请日：2010-02-23

申请人： Michael Richter ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Thomas Hein ,  Andreas Schneider

发明人： Michael Richter ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Thomas Hein ,  Andreas Schneider

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087

摘要： A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.

摘要翻译： 一种半导体存储器，包括设置在集成电路上的多个存储体，每个存储体包括存储单元阵列，其中多个存储体的存储单元的第一部分具有第一存取速度和第二部分存储单元 多个存储器组具有第二存取速度，其中第一存取速度与第二存取速度不同。

公开(公告)号：US08271827B2

公开(公告)日：2012-09-18

申请号：US11953694

申请日：2007-12-10

申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

IPC分类号： G06F1/10

CPC分类号： G06F13/4243

摘要： A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

摘要翻译： 一种包括中央处理单元的系统，第一存储器通道被配置为将中央处理单元耦合到第一半导体存储器单元，其中第一存储器通道被配置为以第一时钟频率进行计时，并且配置第二存储器通道 将所述中央处理单元耦合到第二半导体存储器单元，其中所述第二存储器通道被配置或配置为以小于所述第一时钟频率的第二时钟频率进行定时。

公开(公告)号：US08125812B2

公开(公告)日：2012-02-28

申请号：US12058899

申请日：2008-03-31

申请人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz

发明人： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz

IPC分类号： G11C5/02

CPC分类号： G11C7/22 ,  G06F1/10 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

摘要： Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.

摘要翻译： 用于发送输出有用信号和输出时钟信号的方法和装置。 有用的信号和时钟信号从发射机经由第一线对和第二线对发射到接收机。 第一有用信号以第一线对的电位之间的调制差的形式发送。 第二有用信号以第二线对的电位之间的调制差的形式传输。 时钟信号以第一线对的电位的平均值与第二线对的电位的平均值之间的调制差的形式发送。

公开(公告)号：US08031539B2

公开(公告)日：2011-10-04

申请号：US12248759

申请日：2008-10-09

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G11C7/00

CPC分类号： G11C5/00 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.

摘要翻译： 在一个实施例中，存储器件包括时钟产生单元，其被配置为产生读取时钟信号，所述时钟产生单元连接到被配置为发送读取时钟信号的第一时钟信号触点，并且所述时钟产生单元连接到数据 信号触点被配置为发送数据信号，所述存储器件被配置为相对于读时钟信号以相位和频率精确（源同步）方式发送数据信号。

公开(公告)号：US07908232B2

公开(公告)日：2011-03-15

申请号：US11844791

申请日：2007-08-24

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G06F15/18

CPC分类号： G06F13/1684

摘要： A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.

摘要翻译： 训练存储器装置中的连接的方法包括训练存储器部分和控制器的接收器部分之间的连接，用于在存储器装置的元件之间的基本上所有其他连接的训练之前或同时进行控制， 训练有素

公开(公告)号：US07771206B2

公开(公告)日：2010-08-10

申请号：US12209019

申请日：2008-09-11

申请人： Michael Bruennert ,  Peter Gregorius ,  Georg Braun ,  Andreas Gärtner ,  Hermann Ruckerbauer ,  George William Alexander ,  Johannes Stecker

发明人： Michael Bruennert ,  Peter Gregorius ,  Georg Braun ,  Andreas Gärtner ,  Hermann Ruckerbauer ,  George William Alexander ,  Johannes Stecker

IPC分类号： H01R12/00

CPC分类号： H05K1/141 ,  H05K1/144 ,  H05K3/326 ,  H05K3/328 ,  H05K3/366 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/10159 ,  H05K2203/049

摘要： Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.

摘要翻译： 公开了水平双列直插式存储器模块。 在一个实施例中，存储器模块包括电路板，附接到电路板的顶表面的多个存储器芯片以及设置在电路板的背面下方并远离存储器芯片延伸的多个连接器触点， 连接器触点电耦合到存储器芯片，背面与电路板的顶表面相对。