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    Digital memory and method of operation for a digital memory
    3.
    发明授权
    Digital memory and method of operation for a digital memory 有权
    数字存储器和数字存储器的操作方法

    公开(公告)号：US06208562B1

    公开(公告)日：2001-03-27

    申请号：US09536029

    申请日：2000-03-27

    申请人： Martin Zibert ,  Bret Johnson

    发明人： Martin Zibert ,  Bret Johnson

    IPC分类号： G11C700

    CPC分类号： G11C29/46

    摘要： The digital memory has at least one data line and address lines. It also has a switching unit that, in an active state, inverts signals on the data line or on at least one of the address lines and that, in an inactive state, leaves the signals unchanged. In a first operating mode, the switching unit is in the same state for writing and reading. In a second operating mode, the switching unit is in respectively opposite states for writing and for reading.

    摘要翻译： 数字存储器具有至少一条数据线和地址线。 它还具有开关单元，其处于活动状态，使数据线上或至少一个地址线上的信号反相，并且在非活动状态下使信号保持不变。 在第一操作模式中，切换单元处于用于写入和读取的相同状态。 在第二操作模式中，切换单元分别处于写入和读取的相反状态。

    Method for reading and refreshing a dynamic semiconductor memory
    4.
    发明授权
    Method for reading and refreshing a dynamic semiconductor memory 有权
    读取和刷新动态半导体存储器的方法

    公开(公告)号：US5978296A

    公开(公告)日：1999-11-02

    申请号：US205624

    申请日：1998-12-04

    申请人： Martin Zibert

    发明人： Martin Zibert

    IPC分类号： G11C11/401 ,  G11C11/406

    CPC分类号： G11C11/406

    摘要： The invention relates to a method for reading and refreshing data contents of a dynamic semiconductor memory having many volatile memory cells disposed in columns and rows in a matrix. The reading of the data contents from addressed memory cells is done with the aid of at least two data buses. The data contents are applied word by word to the data buses and a refreshing of the data contents of the memory cells is effected by a refresh pulse. According to the invention, it is provided that the data words applied to the data buses after the triggering of the refresh pulse are maintained for a predetermined period of time on all the data buses and only after that are the data words removed by of a shutoff pulse.

    摘要翻译： 本发明涉及一种用于读取和刷新动态半导体存储器的数据内容的方法，该动态半导体存储器具有以矩阵形式列和列排列的许多易失性存储单元。 借助于至少两条数据总线，从寻址的存储单元读取数据内容。 数据内容逐字逐句地应用于数据总线，并通过刷新脉冲来实现对存储器单元的数据内容的刷新。 根据本发明，提供了在触发刷新脉冲之后施加到数据总线的数据字在所有数据总线上保持预定时间段，并且之后是通过关闭去除的数据字 脉冲。

    CMOS buffer circuit with controlled current source
    5.
    发明授权
    CMOS buffer circuit with controlled current source 失效
    CMOS缓冲电路具有受控电流源

    公开(公告)号：US5455527A

    公开(公告)日：1995-10-03

    申请号：US123647

    申请日：1993-09-17

    申请人： Brian Murphy ,  Martin Zibert

    发明人： Brian Murphy ,  Martin Zibert

    IPC分类号： G06F3/00 ,  H03K3/353 ,  H03K3/3565 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/0175

    CPC分类号： H03K19/00361 ,  H03K19/01855 ,  H03K3/3565

    摘要： An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source. The MOS-transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS-transistor is conducting.

    摘要翻译： 集成缓冲电路结构具有串联连接的两个反相器。 电路节点位于两个逆变器之间。 至少第一个逆变器是用于输入信号IN的CMOS反相器。 CMOS反相器具有连接到第一电源电位的n沟道晶体管。 p沟道晶体管的源极与恒流源连接。 第一使能晶体管连接在第一反相器的n沟道晶体管和电路节点之间。 第二使能晶体管与由第一反相器的恒流源和p沟道晶体管形成的配置并联连接。 使能晶体管的栅极与缓冲电路的使能输入相连。 存在于使能输入端的使能信号使得可以在具有已知过程的干扰的情况下停用缓冲电路。 MOS晶体管可以用作恒流源。 然后将MOS晶体管连接到第二电源电位，并且其栅极处于参考电位，其值总是具有相对于第二电源电位的恒定差值。 在运行期间，MOS晶体管导通。

    MOS output buffer circuit with controlled current source
    6.
    发明授权
    MOS output buffer circuit with controlled current source 失效
    MOS输出缓冲电路具有受控电流源

    公开(公告)号：US5386157A

    公开(公告)日：1995-01-31

    申请号：US123648

    申请日：1993-09-17

    申请人： Brian Murphy ,  Martin Zibert

    发明人： Brian Murphy ,  Martin Zibert

    IPC分类号： G06F3/00 ,  H03K3/353 ,  H03K3/3565 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/017

    CPC分类号： H03K19/01855 ,  H03K19/00361 ,  H03K3/3565

    摘要： An integrated buffer circuit configuration has two inverters which are mutually connected in series. The first inverter includes an n-channel transistor and a constant current source. The source of the n-channel transistor is connected to a first supply potential. The drain of the transistor is connected with the constant current source through a first enable transistor. A second enable transistor is connected parallel to the constant current source. The gates of enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS transistor may function as the constant current source. The MOS transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS transistor is conducting.

    摘要翻译： 集成缓冲电路结构具有串联连接的两个反相器。 第一反相器包括n沟道晶体管和恒流源。 n沟道晶体管的源极连接到第一电源电位。 晶体管的漏极通过第一使能晶体管与恒流源连接。 第二使能晶体管与恒流源并联连接。 使能晶体管的栅极与缓冲电路的使能输入相连接。 存在于使能输入端的使能信号使得可以在具有已知过程的干扰的情况下停用缓冲电路。 MOS晶体管可以用作恒流源。 然后，MOS晶体管连接到第二电源电位，并且其栅极处于参考电位，其值总是具有相对于第二电源电位的恒定差值。 在运行期间，MOS晶体管导通。