公开(公告)号：US20160004296A1

公开(公告)日：2016-01-07

申请号：US14322185

申请日：2014-07-02

申请人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

发明人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/171

摘要： Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了与自主C状态机制和计算引擎对准相关的方法和设备，以提高处理器功率效率。 一个实施例基于用于进入和退出包装C状态的能量消耗值，半导体封装在包装C中保持在预先状态的时间量以及一个或多个盈亏平衡时间来确定半导体封装是否应该进入封装C状态 各种封装C状态之间的点。 另一个实施例检测处理器的成像计算单元相对于处理器的一个或多个其它计算单元进入低功耗状态的延迟。 该逻辑使成像计算单元响应于延迟的检测而进入低功耗状态。 还公开并要求保护其他实施例。

公开(公告)号：US20160134521A1

公开(公告)日：2016-05-12

申请号：US14895949

申请日：2013-06-18

申请人： Roy SHOR ,  Ori GOREN ,  Amit GUR ,  Gad YUVAL ,  FREESCALE SEMICONDUCTOR, INC.

发明人： ROY SHOR ,  ORI GOREN ,  AMIT GUR ,  GAD YUVAL

IPC分类号： H04L12/721

CPC分类号： H04L45/38 ,  H04L12/6418 ,  H04L49/90 ,  H04L49/9078

摘要： A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

摘要翻译： 处理器设备处理移动通信系统中的无线电信号的数据样本。 对所有样品执行快速流程，并且在样品子集上间隔执行批处理。 该装置具有用于通过本地缓冲存储器，到系统存储器的存储器接口和用于控制数据样本存储在缓冲存储器中的存储器控​​制器来执行流程处理的处理器。 处理器确定本地缓冲存储器中的数据采样是否是子集的一部分，如果不是，则在执行流程之后使其无效。 存储器控制器通过将从本地缓冲存储器无效的数据样本传送到系统存储器，并使处理的样本无效，在本地缓冲器中提供空闲的存储空间。 有利地，本地缓冲器可能相对较小，而传送到系统存储器的数据量是有限的。

公开(公告)号：US20150347332A1

公开(公告)日：2015-12-03

申请号：US14759203

申请日：2013-01-10

申请人： ROY SHOR ,  NIR BARUCH ,  ORI GOREN ,  AMIT GUR

发明人： ROY SHOR ,  NIR BARUCH ,  ORI GOREN ,  AMIT GUR

IPC分类号： G06F13/28 ,  G06F13/24 ,  G06F13/42

CPC分类号： G06F13/287 ,  G06F13/24 ,  G06F13/4282 ,  H04W88/085

摘要： A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

摘要翻译： 公共无线电接口CPRI，处理器的通道控制器，在时分双工，TDD系统中，所述CPRI通道控制器包括：直接存储器访问（或多于一个），DMA，通过一个或多个存储器连接到存储器的控制器 交换结构经由所述处理器的内部系统总线执行读取或/和写入存储器访问事务，其中所述DMA控制器适于为由所述处理器计数的每个完成的存储器访问RX / TX事务产生RX / TX事务中断 当RX / TX TDD时隙已经终止时提供TDD时隙感知中断的相应的事务计数器，其中所述DMA控制器具有适于将所述存储器访问事务引导到所述存储器的转向控制或者将 由所述交换结构合理地阻止所述TDD时隙感知中断以节省所述处理器的内部系统总线的带宽BW。