公开(公告)号：US09935873B2

公开(公告)日：2018-04-03

申请号：US14895949

申请日：2013-06-18

申请人： Roy Shor ,  Ori Goren ,  Amit Gur ,  Gad Yuval

发明人： Roy Shor ,  Ori Goren ,  Amit Gur ,  Gad Yuval

IPC分类号： H04L12/721 ,  H04L12/861 ,  H04L12/64

CPC分类号： H04L45/38 ,  H04L12/6418 ,  H04L49/90 ,  H04L49/9078

摘要： A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

公开(公告)号：US20160004296A1

公开(公告)日：2016-01-07

申请号：US14322185

申请日：2014-07-02

申请人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

发明人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/171

摘要： Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了与自主C状态机制和计算引擎对准相关的方法和设备，以提高处理器功率效率。 一个实施例基于用于进入和退出包装C状态的能量消耗值，半导体封装在包装C中保持在预先状态的时间量以及一个或多个盈亏平衡时间来确定半导体封装是否应该进入封装C状态 各种封装C状态之间的点。 另一个实施例检测处理器的成像计算单元相对于处理器的一个或多个其它计算单元进入低功耗状态的延迟。 该逻辑使成像计算单元响应于延迟的检测而进入低功耗状态。 还公开并要求保护其他实施例。

公开(公告)号：US20150347332A1

公开(公告)日：2015-12-03

申请号：US14759203

申请日：2013-01-10

申请人： ROY SHOR ,  NIR BARUCH ,  ORI GOREN ,  AMIT GUR

发明人： ROY SHOR ,  NIR BARUCH ,  ORI GOREN ,  AMIT GUR

IPC分类号： G06F13/28 ,  G06F13/24 ,  G06F13/42

CPC分类号： G06F13/287 ,  G06F13/24 ,  G06F13/4282 ,  H04W88/085

摘要： A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

摘要翻译： 公共无线电接口CPRI，处理器的通道控制器，在时分双工，TDD系统中，所述CPRI通道控制器包括：直接存储器访问（或多于一个），DMA，通过一个或多个存储器连接到存储器的控制器 交换结构经由所述处理器的内部系统总线执行读取或/和写入存储器访问事务，其中所述DMA控制器适于为由所述处理器计数的每个完成的存储器访问RX / TX事务产生RX / TX事务中断 当RX / TX TDD时隙已经终止时提供TDD时隙感知中断的相应的事务计数器，其中所述DMA控制器具有适于将所述存储器访问事务引导到所述存储器的转向控制或者将 由所述交换结构合理地阻止所述TDD时隙感知中断以节省所述处理器的内部系统总线的带宽BW。

公开(公告)号：US20090063779A1

公开(公告)日：2009-03-05

申请号：US11849375

申请日：2007-09-04

申请人： Shai Koren ,  Alon Eldar ,  Amit Gur ,  Itay Peled ,  Rotem Porat

发明人： Shai Koren ,  Alon Eldar ,  Amit Gur ,  Itay Peled ,  Rotem Porat

IPC分类号： G06F12/08

CPC分类号： G06F12/0857 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1012

摘要： A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.

摘要翻译： 一种高速缓冲存储器，包括：（i）连接到多址接入发生器的仲裁器，所述仲裁器适于从多个接入发生器接收不同类型的接入请求，并且每个仲裁周期选择单个接入请求; （ii）流水线级序列，该序列包括连接到仲裁器的输入流水线级; 和（iii）连接到流水线级序列的多个高速缓存资源; 其中每个高速缓存资源只能由流水线级的序列的一小部分读取，并且可以仅被写入流水线级序列的一小部分。

公开(公告)号：US06944755B2

公开(公告)日：2005-09-13

申请号：US09910554

申请日：2001-07-20

申请人： Amit Gur ,  Haim Rizi ,  Dror Halahmi

发明人： Amit Gur ,  Haim Rizi ,  Dror Halahmi

IPC分类号： G06F5/01 ,  G06F9/30 ,  G06F9/308 ,  G06F9/315 ,  G06F15/00 ,  H04B1/38

CPC分类号： G06F5/01 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109

摘要： A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.

摘要翻译： 电路从源寄存器中选择性地从不同位置提取位，并以目的寄存器的一侧的逻辑顺序加载它们。 寄存器分为子集。 每个子集中的所有传输比特都按照逻辑顺序排列在一边。 这些子集是配对的。 来自一对的比特被移位等于来自另一对的非传输比特的量，然后与来自另一对的比特组合，以形成一组新的比特，并且以逻辑顺序。 一对移位中的一个位的位和与该对中的另一个组合的过程继续进行，直到来自源寄存器的所有传输位在一侧为一组并且以逻辑顺序。

公开(公告)号：US20150081934A1

公开(公告)日：2015-03-19

申请号：US14028489

申请日：2013-09-16

申请人： Vinay Gupta ,  Nir Baruch ,  Amit Gur

发明人： Vinay Gupta ,  Nir Baruch ,  Amit Gur

IPC分类号： G06F5/16

CPC分类号： G06F13/1626 ,  G06F1/12 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1689

摘要： A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.

摘要翻译： 用于同步和重新排序在与第一和第二设备接口相关联的第一和第二时钟域之间传输的数据的系统分别包括分离器，仲裁器，事务管理器和读取数据缓冲器。 分离器从第一设备接口的一个或多个数据输入端口接收父读请求，并将其分解成一个或多个读请求。 仲裁器接收一个或多个读取请求，并选择一个读取请求并将其发送到事务管理器。 事务管理器将一个条目分配给读取请求，然后读取请求被发送到读取数据缓冲区。 此后，读取的数据缓冲器将读取的请求发送到第二设备接口，并将接收到的响应数据发送到第一设备接口。

公开(公告)号：US06848030B2

公开(公告)日：2005-01-25

申请号：US09909562

申请日：2001-07-20

申请人： Yakov Tokar ,  Amit Gur ,  Jacob Efrat ,  Doron Schupper

发明人： Yakov Tokar ,  Amit Gur ,  Jacob Efrat ,  Doron Schupper

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862

摘要： A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.

摘要翻译： 处理系统具有处理器，高速缓存和提取单元。 如果高速缓存中存在缺失，则提取单元为缓存中的未命中生成提取地址，以便从外部存储器检索所请求的数据，并将数据提供给处理器并将数据加载到一行中的位置 在缓存中。 提取单元还生成与获取地址连续的地址的附加预取地址。 对于与提取地址连续的高速缓存中的行中的所有位置，继续生成预取地址。 如果另一个请求到达不是已经生成的预取地址的一部分，则预取地址的生成将被停止。 此外，如果外部存储器可以处理这种终止，那么未完成的预取将被终止。

公开(公告)号：US09824044B2

公开(公告)日：2017-11-21

申请号：US14759203

申请日：2013-01-10

申请人： Roy Shor ,  Nir Baruch ,  Ori Goren ,  Amit Gur

发明人： Roy Shor ,  Nir Baruch ,  Ori Goren ,  Amit Gur

IPC分类号： G06F13/28 ,  G06F13/42 ,  G06F13/24 ,  H04W88/08

CPC分类号： G06F13/287 ,  G06F13/24 ,  G06F13/4282 ,  H04W88/085

摘要： A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

公开(公告)号：US08006015B2

公开(公告)日：2011-08-23

申请号：US12514007

申请日：2006-11-08

申请人： Yaki Devilla ,  Moshe Anschel ,  Kostantin Godin ,  Amit Gur ,  Itay Peled

发明人： Yaki Devilla ,  Moshe Anschel ,  Kostantin Godin ,  Amit Gur ,  Itay Peled

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/00 ,  G06F9/34

CPC分类号： G06F13/36 ,  G06F13/1605

摘要： A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.

摘要翻译： 一种用于管理访问请求的装置和方法，所述方法包括：（i）从耦合到主总线的主组件接收多个访问请求以通过流水线从属总线访问从组件; 在以下情况下确认所接收的访问请求：（a）至少从访问请求的最后确认过去的访问间请求延迟时间; （b）等待确认的访问请求的数量低于阈值; 其中所述阈值响应于所述流水线从属总线的流水线深度被确定; （c）接收到的访问请求是有效的; 其中访问请求的有效性响应于访问请求取消请求的接收; 以及（ii）响应于至少一个确认的访问请求，从所述从属组件提供信息。

公开(公告)号：US20110022800A1

公开(公告)日：2011-01-27

申请号：US12934275

申请日：2008-04-11

申请人： Rotem Porat ,  Moshe Anschel ,  Alon Eldar ,  Amit Gur ,  Shai Koren ,  Itay Peled

发明人： Rotem Porat ,  Moshe Anschel ,  Alon Eldar ,  Amit Gur ,  Shai Koren ,  Itay Peled

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/126

摘要： A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.

摘要翻译： 一种用于选择高速缓存方式的方法，所述方法包括：从用于接收数据单元的高速缓存模块的多个高速缓存路径中选择最初选择的高速缓存路; 所述方法的特征在于包括：从位于与所述第一高速缓存方式预定义的偏移量的至少一组高速缓存路径中，搜索所述初始选择的高速缓存方式是否被锁定，以解锁的高速缓存方式。