公开(公告)号：US10334008B2

公开(公告)日：2019-06-25

申请号：US14899132

申请日：2013-07-04

Applicant: Roy Shor ,  Ori Goren ,  Avraham Horn ,  Avraham Rabinovich

Inventor： Roy Shor ,  Ori Goren ,  Avraham Horn ,  Avraham Rabinovich

IPC: H04L29/06 ,  H04L29/08 ,  H04L29/10 ,  H04W76/00 ,  H04W88/08

Abstract: Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

公开(公告)号：US20160134521A1

公开(公告)日：2016-05-12

申请号：US14895949

申请日：2013-06-18

Applicant: Roy SHOR ,  Ori GOREN ,  Amit GUR ,  Gad YUVAL ,  FREESCALE SEMICONDUCTOR, INC.

Inventor： ROY SHOR ,  ORI GOREN ,  AMIT GUR ,  GAD YUVAL

IPC: H04L12/721

CPC classification number: H04L45/38 ,  H04L12/6418 ,  H04L49/90 ,  H04L49/9078

Abstract: A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

Abstract translation: 处理器设备处理移动通信系统中的无线电信号的数据样本。 对所有样品执行快速流程，并且在样品子集上间隔执行批处理。 该装置具有用于通过本地缓冲存储器，到系统存储器的存储器接口和用于控制数据样本存储在缓冲存储器中的存储器控​​制器来执行流程处理的处理器。 处理器确定本地缓冲存储器中的数据采样是否是子集的一部分，如果不是，则在执行流程之后使其无效。 存储器控制器通过将从本地缓冲存储器无效的数据样本传送到系统存储器，并使处理的样本无效，在本地缓冲器中提供空闲的存储空间。 有利地，本地缓冲器可能相对较小，而传送到系统存储器的数据量是有限的。

公开(公告)号：US09635710B2

公开(公告)日：2017-04-25

申请号：US14776746

申请日：2013-03-28

Applicant: Roy Shor ,  Ori Goren ,  Avraham Horn

Inventor： Roy Shor ,  Ori Goren ,  Avraham Horn

IPC: H04W4/00 ,  H04W88/08

CPC classification number: H04W88/085

Abstract: An apparatus for facilitating the re-distribution of processing load between a plurality of radio equipment controllers arranged in a daisy chain configuration on a Common Public Radio Interface. The apparatus may be included in each REC and has two framers which may co-operate to forward IQ data of antenna carriers received on a downlink from a preceding REC to a subsequent REC in the chain and a DMA module or channel which can read IQ data from a system memory for onward transmission. In a re-allocation mode, the framer may be reconfigured so that an AxC initially allocated to a preceding REC for processing may be instead, accessed by a second (usually redundant) transmit DMA module included in the apparatus from system memory and transferred to the framer for onward transmission.

公开(公告)号：US10225196B2

公开(公告)日：2019-03-05

申请号：US14765841

申请日：2013-02-15

Applicant: Roy Shor ,  Ori Goren ,  Avraham Horn ,  John Vaglica ,  Tuongvu Nguyen

Inventor： Roy Shor ,  Ori Goren ,  Avraham Horn ,  John Vaglica ,  Tuongvu Nguyen

IPC: H04L12/833 ,  H04L29/08 ,  H04W72/04

Abstract: A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

公开(公告)号：US20160150558A1

公开(公告)日：2016-05-26

申请号：US14899137

申请日：2013-07-04

Applicant: Roy SHOR ,  Ori GOREN ,  Avraham HORN ,  Yaei KAHIL ,  Shay SHPRITZ

Inventor： Roy SHOR ,  Ori GOREN ,  Avraham HORN ,  Yael KAHIL ,  Shay SHPRITZ

IPC: H04W72/12 ,  H04L12/721

CPC classification number: H04W72/1263 ,  H04L45/66 ,  H04W88/085

Abstract: Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected control data arranged in packets to a controller, the selected control data being streamed between other radio units via the common public radio interface. In the radio unit, the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller via the packet based serial interface.

Abstract translation: 在移动通信系统中的基站中的无线电单元之间的接口使用通用公共无线电接口CPRI来流式传输IQ数据样本和布置在车道中的控制数据。 现在另外使用单独的串行接口sRIO来将选择的以分组排列的控制数据传送到控制器，所选择的控制数据经由公共无线电接口在其它无线电单元之间流传输。 在无线电单元中，所选择的控制数据被布置成要经由串行接口发送的分组，反之亦然，经由串行接口接收的分组中排列的所选择的控制数据被布置在要流式传输的通道中。 有利的是，流式CPRI接口的控制数据通过基于分组的串行接口无缝地传送到控制器。

公开(公告)号：US20160128040A1

公开(公告)日：2016-05-05

申请号：US14889485

申请日：2013-05-29

Applicant: Roy Shor ,  Ori Goren ,  Avraham Horn

Inventor： Roy Shor ,  Ori Goren ,  Avraham Horn

IPC: H04W72/04 ,  H04L27/233

CPC classification number: H04W72/044 ,  H04L27/2338 ,  H04W88/085 ,  H04W88/181 ,  H04W92/00

Abstract: Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

Abstract translation: 描述了根据移动通信系统中的基站中的公共无线电接口的公共接口。 接口包括用于对传统数据样本进行速率转换的转换过程。 首先，将预定数量的遗留数据样本转换为频域中的频率采样，然后根据4G数据格式的相关采样率将频率采样零填充以扩展频率范围，然后转换成多个数据 相关采样率样本。 相关采样率是S / K乘以4G数据格式的基本帧速率，S个样本被分配给K个帧，K和S是整数，K是8或更小。 有利的是，避免了将大量遗留样本分配到4G帧的大型缓冲器。

公开(公告)号：US10342032B2

公开(公告)日：2019-07-02

申请号：US14899137

申请日：2013-07-04

Applicant: Roy Shor ,  Ori Goren ,  Avraham Horn ,  Yael Kahil ,  Shay Shpritz

Inventor： Roy Shor ,  Ori Goren ,  Avraham Horn ,  Yael Kahil ,  Shay Shpritz

IPC: H04W72/12 ,  H04W88/08 ,  H04L12/721

Abstract: Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected control data arranged in packets to a controller, the selected control data being streamed between other radio units via the common public radio interface. In the radio unit, the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller via the packet based serial interface.

公开(公告)号：US09824044B2

公开(公告)日：2017-11-21

申请号：US14759203

申请日：2013-01-10

Applicant: Roy Shor ,  Nir Baruch ,  Ori Goren ,  Amit Gur

Inventor： Roy Shor ,  Nir Baruch ,  Ori Goren ,  Amit Gur

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/24 ,  H04W88/08

CPC classification number: G06F13/287 ,  G06F13/24 ,  G06F13/4282 ,  H04W88/085

Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

公开(公告)号：US20160142458A1

公开(公告)日：2016-05-19

申请号：US14899132

申请日：2013-07-04

Applicant: ROY SHOR ,  ORI GOREN ,  AVRAHAM HORN ,  AVRAHAM RABINOVICH

Inventor： ROY SHOR ,  ORI GOREN ,  AVRAHAM HORN ,  AVRAHAM RABINOVICH

IPC: H04L29/06

CPC classification number: H04L65/60 ,  H04L29/08 ,  H04L29/10 ,  H04W76/00 ,  H04W88/085

Abstract: Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

Abstract translation: 在移动通信系统中的基站中的无线电单元之间的接口使用普通的公共无线电接口CPRI来流式化布置在车道中的IQ数据样本。 现在另外使用单独的串行接口sRIO来传送分组中排列的所选数据样本，所选择的样本对应于通过公共无线电接口在其它无线电单元之间流动的所选择的通道。 在无线电单元中，所选择的数据样本被布置成要经由串行接口发送的分组，反之亦然，经由串行接口接收的分组中排列的所选数据样本被布置在通道中。 耦合到CPRI的系统定时器产生用于控制sRIO接口的时基，以使其同步。 有利的是，使用基于分组的串行接口来扩展流式CPRI接口的数据样本传送容量。

公开(公告)号：US20150372930A1

公开(公告)日：2015-12-24

申请号：US14765841

申请日：2013-02-15

Applicant: Roy SHOR ,  Ori GOREN ,  Avraham HORN ,  John VAGLICA ,  Tuongvu NGUYEN

Inventor： ROY SHOR ,  ORI GOREN ,  AVRAHAM HORN ,  JOHN VAGLICA ,  TUONGVU NGUYEN

IPC: H04L12/833 ,  H04L29/08 ,  H04W72/04

CPC classification number: H04L47/2458 ,  H04L69/324 ,  H04W72/04

Abstract: A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

Abstract translation: 用于通过CPRI（公共无线电接口）通信的节点的系统允许以菊花链配置的每个网络节点无缝地管理用于上行链路和下行链路的控制和管理HDLC（高速数据链路控制）信道。 连接通过软复位流保持活动。 接收到的HDLC数据包可以被提取以供本地节点使用。 本地生成的数据包可以插入到数据链路层的数据包数据流中，以便通过CPRI向前传输。 系统在保存在本地节点的缓冲器中的本地产生的分组数据和从远程节点接收并保存在本地节点中的第一先进先出缓冲器中的本地产生的分组数据之间进行仲裁，以在仲裁之后向后发送到后续节点。 远程分组数据优先。