专利检索 ap:("JONG WON KIM" OR "SEUNG HYUN LIM" OR "CHANG SEOK KANG" OR "YOUNG WOO PARK" OR "DAE HOON BAE" OR "DONG SEOG EUN" OR "WOO SUNG LEE" OR "JAE DUK LEE" OR "JAE WOO LIM" OR "HANMEI CHOI") AND inv:"DAE HOON BAE" 第 1 页

1.

发明申请
VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS 审中-公开

公开(公告)号：US20170294443A1

公开(公告)日：2017-10-12

申请号：US15626395

申请日：2017-06-19

申请人： JONG WON KIM , SEUNG HYUN LIM , CHANG SEOK KANG , YOUNG WOO PARK , DAE HOON BAE , DONG SEOG EUN , WOO SUNG LEE , JAE DUK LEE , JAE WOO LIM , HANMEI CHOI

发明人： JONG WON KIM , SEUNG HYUN LIM , CHANG SEOK KANG , YOUNG WOO PARK , DAE HOON BAE , DONG SEOG EUN , WOO SUNG LEE , JAE DUK LEE , JAE WOO LIM , HANMEI CHOI

IPC分类号： H01L27/11565 , H01L27/11524 , H01L27/11556 , H01L29/04 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L27/11519 , H01L27/11529

CPC分类号： H01L27/11565 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/04

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.