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公开(公告)号:US20170294443A1
公开(公告)日:2017-10-12
申请号:US15626395
申请日:2017-06-19
申请人: JONG WON KIM , SEUNG HYUN LIM , CHANG SEOK KANG , YOUNG WOO PARK , DAE HOON BAE , DONG SEOG EUN , WOO SUNG LEE , JAE DUK LEE , JAE WOO LIM , HANMEI CHOI
发明人: JONG WON KIM , SEUNG HYUN LIM , CHANG SEOK KANG , YOUNG WOO PARK , DAE HOON BAE , DONG SEOG EUN , WOO SUNG LEE , JAE DUK LEE , JAE WOO LIM , HANMEI CHOI
IPC分类号: H01L27/11565 , H01L27/11524 , H01L27/11556 , H01L29/04 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L27/11519 , H01L27/11529
CPC分类号: H01L27/11565 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/04
摘要: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
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公开(公告)号:US20170170191A1
公开(公告)日:2017-06-15
申请号:US15252740
申请日:2016-08-31
申请人: BYOUNG IL LEE , JOONG SHIK SHIN , DONG SEOG EUN , KYUNG JUN SHIN , HYUN KOOK LEE
发明人: BYOUNG IL LEE , JOONG SHIK SHIN , DONG SEOG EUN , KYUNG JUN SHIN , HYUN KOOK LEE
IPC分类号: H01L27/115 , H01L27/02
CPC分类号: H01L27/11582 , H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.
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