公开(公告)号：US20170294443A1

公开(公告)日：2017-10-12

申请号：US15626395

申请日：2017-06-19

申请人： JONG WON KIM ,  SEUNG HYUN LIM ,  CHANG SEOK KANG ,  YOUNG WOO PARK ,  DAE HOON BAE ,  DONG SEOG EUN ,  WOO SUNG LEE ,  JAE DUK LEE ,  JAE WOO LIM ,  HANMEI CHOI

发明人： JONG WON KIM ,  SEUNG HYUN LIM ,  CHANG SEOK KANG ,  YOUNG WOO PARK ,  DAE HOON BAE ,  DONG SEOG EUN ,  WOO SUNG LEE ,  JAE DUK LEE ,  JAE WOO LIM ,  HANMEI CHOI

IPC分类号： H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11529

CPC分类号： H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US20130099090A1

公开(公告)日：2013-04-25

申请号：US13616205

申请日：2012-09-14

申请人： YU JIN PARK ,  KWI SUNG YOO ,  SEUNG HYUN LIM

发明人： YU JIN PARK ,  KWI SUNG YOO ,  SEUNG HYUN LIM

IPC分类号： H03M1/14 ,  H01L27/146

CPC分类号： H03M1/16 ,  H03M1/123 ,  H03M1/56 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/378

摘要： A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.

摘要翻译： 两步模拟数字转换电路包括比较器，高位计数器和脉冲残差转换单元。 比较器被配置为比较斜坡信号和输入信号，并输出结果比较信号。 高位计数器被配置为接收比较信号和时钟信号，并且输出对应于斜坡信号的生成时间点和时钟信号的第一边沿之间的第一时间间隔的高位值， 紧接在比较信号的状态转变时间点之前的时钟信号。 脉冲残余转换单元被配置为接收比较信号和时钟信号，并且输出与时钟信号的第一边沿和比较信号的状态转移时间点之间的第二时间间隔相对应的较低位值。