公开(公告)号：US09172521B2

公开(公告)日：2015-10-27

申请号：US13399194

申请日：2012-02-17

申请人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

发明人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC分类号： G06F19/00 ,  H04L5/14 ,  H04L25/03

CPC分类号： H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

公开(公告)号：US08121803B2

公开(公告)日：2012-02-21

申请号：US12360029

申请日：2009-01-26

申请人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

发明人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC分类号： G06F19/00

CPC分类号： H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

摘要翻译： 用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特征。 关于感测到的特性的信息使用辅助信道反馈到第一分量。 响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。 而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

公开(公告)号：US20090132741A1

公开(公告)日：2009-05-21

申请号：US12360029

申请日：2009-01-26

申请人： JUN KIM ,  Wayne S. Richardson ,  Glenn Chiu

发明人： JUN KIM ,  Wayne S. Richardson ,  Glenn Chiu

IPC分类号： G06F13/14

CPC分类号： H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

摘要翻译： 用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特征。 关于感测到的特性的信息使用辅助信道反馈到第一分量。 响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。 而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

公开(公告)号：US07516029B2

公开(公告)日：2009-04-07

申请号：US10864897

申请日：2004-06-09

申请人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

发明人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC分类号： G06F15/00

CPC分类号： H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

摘要翻译： 用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特征。 关于感测到的特性的信息使用辅助信道反馈到第一分量。 响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。 而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

公开(公告)号：US20120147935A1

公开(公告)日：2012-06-14

申请号：US13399194

申请日：2012-02-17

申请人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

发明人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC分类号： H04B1/38

CPC分类号： H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

摘要翻译： 用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特征。 关于感测到的特性的信息使用辅助信道反馈到第一分量。 响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。 而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

公开(公告)号：US07254075B2

公开(公告)日：2007-08-07

申请号：US10954941

申请日：2004-09-30

申请人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元传送到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

公开(公告)号：US07755968B2

公开(公告)日：2010-07-13

申请号：US11834915

申请日：2007-08-07

申请人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

IPC分类号： G11C8/00

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

摘要翻译： 集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。 存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸 第二种操作模式。 存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

公开(公告)号：US20140003131A1

公开(公告)日：2014-01-02

申请号：US13860825

申请日：2013-04-11

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US20130305074A1

公开(公告)日：2013-11-14

申请号：US13980826

申请日：2012-02-15

申请人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G06F1/32

CPC分类号： G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US07274244B2

公开(公告)日：2007-09-25

申请号：US11123225

申请日：2005-05-06

申请人： Wayne Fang ,  Wayne S. Richardson ,  Kurt T. Knorpp

发明人： Wayne Fang ,  Wayne S. Richardson ,  Kurt T. Knorpp

IPC分类号： H03K17/00

CPC分类号： H03K17/693

摘要： A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.

摘要翻译： 公开了脉冲多路复用输出子系统。 在一个特定示例性实施例中，输出子系统可以包括多个脉冲发生器，第一对晶体管和第二对晶体管，其中第一对晶体管中的每一个耦合到第一对晶体管中的相应一个 多个脉冲发生器，并且其中第二对晶体管中的每一个耦合到第二对多个脉冲发生器中的相应一个。 输出子系统还可以包括第一对电阻负载，其中第一对电阻负载中的每一个耦合到第一对晶体管中的相应一个和第二对晶体管中的相应一个，以及第一电流源 耦合到第一对晶体管和第二对晶体管。