公开(公告)号：US07902930B2

公开(公告)日：2011-03-08

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03K3/03

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20080129392A1

公开(公告)日：2008-06-05

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03B27/00 ,  H03B5/12

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20090134944A1

公开(公告)日：2009-05-28

申请号：US12114705

申请日：2008-05-02

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

摘要翻译： 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US07852165B2

公开(公告)日：2010-12-14

申请号：US12114705

申请日：2008-05-02

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

摘要翻译： 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US20120161832A1

公开(公告)日：2012-06-28

申请号：US13310581

申请日：2011-12-02

申请人： Ja Yol Lee ,  Seong-Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seong-Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/08

CPC分类号： H03L7/0802 ,  H03L7/085 ,  H03L2207/50

摘要： Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.

摘要翻译： 公开了具有模拟相位误差补偿器的分数字数字锁相环。 具有模拟相位误差补偿器的数字锁相环可以通过模拟相位误差补偿器进行分数相位误差检测和补偿，从而降低功耗，功耗噪声和瞬态电流噪声，同时提高相位误差检测分辨率。

公开(公告)号：US08060020B2

公开(公告)日：2011-11-15

申请号：US12628684

申请日：2009-12-01

申请人： Seong Do Kim ,  Ja Yol Lee ,  Jae Hoon Shim ,  Hyun Kyu Yu

发明人： Seong Do Kim ,  Ja Yol Lee ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC分类号： H04B1/00

CPC分类号： H04B1/123

摘要： An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180° from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180° from each other.

摘要翻译： 公开了一种使用选择性频率相位变换器去除干扰信号的装置和方法。 使用选择性频率相位变换器去除干扰信号的装置包括：第一相位转换器，被配置为将接收的RF信号的相位转换为差分地输出具有彼此相差180°的第一和第二信号; 第二相转换器，被配置为接收第一信号并选择性地转换特定频带的相位; 配置为接收所述第二信号并选择性地转换特定频带的相位的第三相位转换器; 定时控制器，被配置为校正来自第二相位转换器的输出和第三相位转换器的输出之间的信号延迟时间; 以及加法器，被配置为将来自第二相位转换器的输出和来自第三相位转换器的输出相加，其中第二和第三相位转换器对第一和第二信号进行相位转换，使得特定频带的信号的相位做 彼此之间没有180°的相位差。

公开(公告)号：US07961038B2

公开(公告)日：2011-06-14

申请号：US12631637

申请日：2009-12-04

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03B1/00

CPC分类号： G05B1/03

摘要： A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

摘要翻译： 提供了数字比例积分环路滤波器。 第一比例放大单元将相位误差值乘以第一比例环路增益，并且第一积分放大单元将相位误差累积值乘以第一积分环路增益。 第二比例放大单元将相位误差值乘以第二比例环路增益，第二积分放大单元将相位误差累积值乘以第二积分环路增益。 第一偏移值生成单元通过从第一比例环增益中减去第二比例环增益并将结果值乘以相位误差平均值来生成第一偏移值，第二偏移值生成单元通过减去第二偏移值生成单位生成第二偏移值 来自第一积分环路增益的第二积分环路增益，并将得到的值乘以相位误差累积平均值。

公开(公告)号：US07999707B2

公开(公告)日：2011-08-16

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US20100134335A1

公开(公告)日：2010-06-03

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US08031009B2

公开(公告)日：2011-10-04

申请号：US12581105

申请日：2009-10-16

申请人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/085 ,  H03L7/095 ,  H03L7/18 ,  H03L7/081

CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。