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公开(公告)号：US06584560B1
公开(公告)日：2003-06-24
申请号：US09552608
申请日：2000-04-19
IPC分类号： G06F15177
CPC分类号： G06F15/177 , G06F9/4405
摘要： A method and system for choosing the control processor for booting a multiprocessor system (10) in accordance with a memory (42). A computer system (10) includes a plurality of computer processors (12). The processors (12) use a memory bus (18) to communicate with the main memory (20). A second bus (30) connects the processors (12) to an interupt controller (34). The second bus (30) includes multiple bus request lines (14). An initialization control circuit (32) also communicates with the second bus (30). Memory (42) in the initialization control circuit (32) holds data identifying at least one of the processors (12) and when power is first provided to the system, the initialization control circuit (32) operates to assert signals on the bus request lines (14) such that the identified processor initializes the computer system.
摘要翻译： 一种用于根据存储器（42）选择用于引导多处理器系统（10）的控制处理器的方法和系统。 计算机系统（10）包括多个计算机处理器（12）。 处理器（12）使用存储器总线（18）与主存储器（20）进行通信。 第二总线（30）将处理器（12）连接到中断控制器（34）。 第二总线（30）包括多个总线请求线（14）。 初始化控制电路（32）还与第二总线（30）通信。 初始化控制电路（32）中的存储器（42）保存识别至少一个处理器（12）的数据，并且当电力首次提供给系统时，初始化控制电路（32）操作以在总线请求线上断言信号 （14），使得所识别的处理器初始化计算机系统。
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公开(公告)号：US07317410B2
公开(公告)日：2008-01-08
申请号：US11340603
申请日：2006-01-27
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M1/20
摘要： A digital modulator includes a quantizer and a mapper. The quantizer converts a dithered signal value to a voltage. The mapper provides a modulated signal based on the voltage received from the quantizer. The mapper may maintain a substantially identical average centroid for modulated signals provided by the mapper. In an aspect, the mapper is included in a feedback of the digital modulator. The digital modulator may include any number of mappers. For example, a mode selection switch may select one of a plurality of mappers to map a voltage level received from the quantizer to a respective digital sequence.
摘要翻译： 数字调制器包括量化器和映射器。 量化器将抖动信号值转换为电压。 映射器基于从量化器接收的电压提供调制信号。 映射器可以维持由映射器提供的调制信号的基本相同的平均质心。 在一方面，映射器被包括在数字调制器的反馈中。 数字调制器可以包括任何数量的映射器。 例如，模式选择开关可以选择多个映射器中的一个，以将从量化器接收的电压电平映射到相应的数字序列。
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公开(公告)号：US06992604B2
公开(公告)日：2006-01-31
申请号：US10791534
申请日：2004-03-03
IPC分类号： H03M7/00
CPC分类号： H03M1/66 , G11B20/10 , G11B20/10037
摘要： Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.
摘要翻译： 提供了一种用于将具有预定输入采样率的数字数据音频数据音频数据转换为模拟数据信号的系统和方法。 一种系统包括数模转换器（DAC），其包括数字处理部分，数字处理部分被配置为接收数字音频数据和定时信息作为输入，所述定时信息表示输入采样率的时基。 数字处理部分被类似地配置为数字处理数字音频数据和定时信息以产生串行输出数据。 DAC还包括被配置为将串行数据转换为模拟格式的模拟处理部分。 数字处理部分根据具有相应时钟速率的至少一个时钟进行操作，其中对应的时钟速率与输入采样率无关。
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4.发明授权Systems and methods for defining and utilizing attributes of a processor resource 失效用于定义和利用处理器资源的属性的系统和方法公开(公告)号：US07296199B1
公开(公告)日：2007-11-13
申请号：US10760736
申请日：2004-01-20
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G06F12/0802 , G11C2029/0407
摘要： Systems and methods define and utilize processor resource attributes. Parameters of a control field for a resource are defined with at least one #define statement within source code, each #define statement having a common format to specify the parameters. The #define statement is processed to include one or more of the parameters in code generating statements within the source code. The source code is compiled into executable code, and the executable code is executed to utilize attributes of the resource.
摘要翻译： 系统和方法定义和利用处理器资源属性。 资源控制字段的参数用源代码中的至少一个#define语句定义，每个#define语句具有通用格式来指定参数。 处理#define语句以在源代码中的代码生成语句中包含一个或多个参数。 源代码被编译成可执行代码，执行可执行代码以利用资源的属性。
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公开(公告)号：US07203227B1
公开(公告)日：2007-04-10
申请号：US10294048
申请日：2002-11-14
申请人： Bruce J. Currivan , Ravi Bhaskaran , Thomas J. Kolze , Kevin Lee Miller , Jeffrey S. Putnam , Fang Lu , Tak K. Lee , Thuji S. Lin , Loke Kun Tan , Gopal Triplicane Venkatesan , Hsin-An Liu , Jonathan S. Min , James P. Cavallo
发明人： Bruce J. Currivan , Ravi Bhaskaran , Thomas J. Kolze , Kevin Lee Miller , Jeffrey S. Putnam , Fang Lu , Tak K. Lee , Thuji S. Lin , Loke Kun Tan , Gopal Triplicane Venkatesan , Hsin-An Liu , Jonathan S. Min , James P. Cavallo
IPC分类号： H04B1/38
CPC分类号： H04L12/2801
摘要： All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.
摘要翻译： 全数字参考频率锁定。 提供全数字方法以在电缆调制解调器通信系统内的一个或多个CM内操作，以将一个或多个CM的上游锁定到从CMTS提供的下游符号时钟。 CM的上游的锁定可以使用至少三种不同的功能中的一种执行：（1）将上游符号时钟相位锁定到下游符号时钟相位，（2）将下游符号时钟相位锁定到前端参考时钟相位 通常为10.24MHz或其整数倍），以及（3）将上游载波频率锁定到下游符号时钟频率。 用于支持所有数字参考频率锁定功能的全数字技术提供了高性能以支持S-CDMA和其他同步调制技术。
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公开(公告)号：US07084800B2
公开(公告)日：2006-08-01
申请号：US10767774
申请日：2004-01-30
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M1/66
摘要： A sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially identical average centroid for each of the possible output waveforms. For at least some of the output waveforms, two or more sets of pulses are provided representing the same waveform but having different centroids. The output is alternated among the available sets of pulses to maintain the desired average centroid over time. Shuffling of the output among the available pulses representing a given waveform may be randomly determined, or the pulses used may be tracked and the output pulses sequentially alternated among the available output pulses. The shuffled mapping method reduces output harmonics compared to conventional static mappers.
摘要翻译： 用于数字音频电路的序列映射电路和方法产生脉冲输出。 随着时间的推移，映射电路为每个可能的输出波形产生具有基本相同的平均质心的脉冲。 对于至少一些输出波形，提供表示相同波形但具有不同质心的两组或多组脉冲。 输出在可用的脉冲组之间交替，以保持期望的平均质心。 表示给定波形的可用脉冲之间的输出的混洗可以是随机确定的，或者可以跟踪使用的脉冲，并且输出脉冲在可用输出脉冲之间顺序交替。 与传统静态映射器相比，混洗映射方法降低了输出谐波。
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公开(公告)号：US07038607B2
公开(公告)日：2006-05-02
申请号：US10767775
申请日：2004-01-30
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M1/66
摘要： A modulator circuit receives a modulator input signal and produces a mapper output signal. The modulator circuit includes a filter circuit that generates an output that is a function of the modulator input signal and of the mapper output signal. A quantizer receives the filter output signal and produces a quantized representation of the filter output signal. A mapper receives the quantizer output and generates the mapper output signal.
摘要翻译： 调制器电路接收调制器输入信号并产生映射器输出信号。 调制器电路包括产生作为调制器输入信号和映射器输出信号的函数的输出的滤波器电路。 量化器接收滤波器输出信号并产生滤波器输出信号的量化表示。 映射器接收量化器输出并产生映射器输出信号。
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公开(公告)号：US20050062622A1
公开(公告)日：2005-03-24
申请号：US10791534
申请日：2004-03-03
CPC分类号： H03M1/66 , G11B20/10 , G11B20/10037
摘要： Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.
摘要翻译： 提供了一种用于将具有预定输入采样率的数字数据音频数据音频数据转换为模拟数据信号的系统和方法。 一种系统包括数模转换器（DAC），其包括数字处理部分，数字处理部分被配置为接收数字音频数据和定时信息作为输入，所述定时信息表示输入采样率的时基。 数字处理部分被类似地配置为数字处理数字音频数据和定时信息以产生串行输出数据。 DAC还包括被配置为将串行数据转换为模拟格式的模拟处理部分。 数字处理部分根据具有相应时钟速率的至少一个时钟进行操作，其中对应的时钟速率与输入采样率无关。
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公开(公告)号：US5825829A
公开(公告)日：1998-10-20
申请号：US497458
申请日：1995-06-30
申请人： Ramin Borazjani , Kevin Lee Miller
发明人： Ramin Borazjani , Kevin Lee Miller
IPC分类号： H04N7/16 , H04B10/20 , H04H20/46 , H04H20/78 , H04H60/94 , H04H60/97 , H04J1/00 , H04J4/00 , H04L5/02 , H04L12/28 , H04L27/18 , H04L27/26 , H04N7/10 , H04L27/20 , H04H1/08
CPC分类号： H04H20/46 , H04H20/78 , H04H60/94 , H04H60/97 , H04J4/005 , H04L12/2801 , H04L27/2627 , H04N7/10
摘要： A multi-channel modulator for the transmission of telephony signals within a broadband communication system. An interpolation module generates processed I and Q signal components by upsampling filtered I and Q signal components. In turn, these processed I and Q signal components output by a filter are passed to a set of channel modulators. Each channel modulator accepts a pair of processed I and Q signal components and, in response, modulates a selected carrier signal with one of the telephony signals to produce a complex modulated signal. An adder module responds to the complex modulated signals by summing the real signal components to produce a real resultant signal, and to sum the imaginary components to produce an imaginary resultant signal. A digital-to-analog converter (DAC) module coverts the real resultant signal and the imaginary resultant signal, which are represented by digital data streams, to analog signals. A transmitter, responsive to the analog signals, transmits the modulated signals within a frequency band of the broadband communications network.
摘要翻译： 一种用于在宽带通信系统内传输电话信号的多信道调制器。 内插模块通过对经滤波的I和Q信号分量进行上采样来产生经处理的I和Q信号分量。 反过来，由滤波器输出的这些经处理的I和Q信号分量被传递到一组信道调制器。 每个信道调制器接受一对经处理的I和Q信号分量，并且作为响应，用电话信号中的一个调制所选择的载波信号以产生复调制信号。 加法器模块通过对实数信号分量进行求和以产生真实的合成信号来对复调制信号进行响应，并将虚分量相加以产生虚数合成信号。 数模转换器（DAC）模块将由数字数据流表示的实际结果信号和虚拟合成信号覆盖到模拟信号。 响应于模拟信号的发射机在宽带通信网络的频带内发送调制信号。
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公开(公告)号：US08571137B2
公开(公告)日：2013-10-29
申请号：US13223094
申请日：2011-08-31
CPC分类号： H04B1/10 , H03M1/0614 , H03M1/68
摘要： Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion.
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