公开(公告)号：US20080056345A1

公开(公告)日：2008-03-06

申请号：US11708557

申请日：2007-02-21

申请人： Jong-Hoon Kim ,  Jae-Jun Lee ,  Kwang-Soo Park

发明人： Jong-Hoon Kim ,  Jae-Jun Lee ,  Kwang-Soo Park

IPC分类号： H03K7/08

CPC分类号： H03M5/145

摘要： Data transmission system and method are provided. The transmission system includes a data converter and data restoring unit. The data converter converts N-bit first data to be transmitted into M-bit second data, where M is greater than N and the second data is arranged in a minimum unit greater than 1, each minimum unit including at least successive data bits having the same phase. The transmitter compresses the second data prior to transmission via a channel having performance characteristics defining a minimum pulse width, and a receiver receives and de-compresses the transmitted second data. The data restoring unit then restores the first data from the second.

摘要翻译： 提供数据传输系统和方法。 传输系统包括数据转换器和数据恢复单元。 数据转换器将要发送的N位第一数据转换成M位第二数据，其中M大于N，第二数据以大于1的最小单位排列，每个最小单位包括至少连续的数据位， 相同阶段 发射机在通过具有定义最小脉冲宽度的性能特征的信道进行传输之前压缩第二数据，并且接收机接收和解压缩传输的第二数据。 数据恢复单元然后从第二数据恢复第一数据。

公开(公告)号：US20080012661A1

公开(公告)日：2008-01-17

申请号：US11797988

申请日：2007-05-09

申请人： Jong-Hoon Kim ,  Jae-Jun Lee ,  Moon-Jung Kim ,  Kwang-Soo Park ,  Young-Chan Jang

发明人： Jong-Hoon Kim ,  Jae-Jun Lee ,  Moon-Jung Kim ,  Kwang-Soo Park ,  Young-Chan Jang

IPC分类号： H03H7/24

CPC分类号： H05K1/0231 ,  H01L23/64 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/09309 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2924/00

摘要： A semiconductor device, a method related to the semiconductor device, and a printed circuit board are disclosed. The semiconductor device includes a chip, a package including a plurality of power voltage terminals and a plurality of ground voltage terminals, wherein the chip is disposed in the package. The semiconductor device further includes an impedance circuit connected between a DC component power voltage terminal and a ground voltage, wherein the DC component power voltage terminal is one of the plurality of power voltage terminals, and an AC component interrupter connected between the DC component power voltage terminal and a power voltage. Both the AC component and a DC component of the power voltage are applied to each of the power voltage terminals except the DC component second power voltage terminal, and the ground voltage is applied to each of the ground voltage terminals.

摘要翻译： 公开了半导体器件，与半导体器件相关的方法和印刷电路板。 半导体器件包括芯片，包括多个电源电压端子和多个接地电压端子的封装，其中芯片设置在封装中。 半导体装置还包括连接在直流分量电源端子和接地电压之间的阻抗电路，其中直流分量电源电压端子是多个电源电压端子中的一个，以及连接在直流分量电源电压 端子和电源电压。 除了直流分量第二电力电压端子之外，将电力电压的交流分量和直流分量都施加到各电力电压端子，并且将接地电压施加到每个接地电压端子。

公开(公告)号：US07778042B2

公开(公告)日：2010-08-17

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K1/11

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US20080247212A1

公开(公告)日：2008-10-09

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07405949B2

公开(公告)日：2008-07-29

申请号：US11603648

申请日：2006-11-22

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K7/14

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US08107271B2

公开(公告)日：2012-01-31

申请号：US11649805

申请日：2007-01-05

申请人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

发明人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

IPC分类号： G11C5/06

CPC分类号： H03H7/38

摘要： A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

摘要翻译： 终端电路连接到接收数据信号的输入缓冲器，并且包括连接到输入缓冲器以用于阻抗匹配的至少一个终端电阻器。 至少一个开关控制输入缓冲器与至少一个终端电阻器中相应的一个之间的连接。 控制信号发生器产生控制信号，用于通过控制至少一个开关中的每个开关来选择性地启用终端电路。 控制信号的输入周期小于或等于数据信号的输入周期。

公开(公告)号：US07495975B2

公开(公告)日：2009-02-24

申请号：US11377665

申请日：2006-03-17

申请人： Jae-Jun Lee ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Kwang-Soo Park

IPC分类号： G11C29/00

CPC分类号： G11C7/1051 ,  G11C5/14 ,  G11C7/1057 ,  H04L25/0278 ,  H04L25/0298

摘要： Provided is a memory system with an inductor. In the memory system, the inductor is connected to an on-die termination unit of a memory chip, thereby realizing constant gain characteristics without respect to a variation in an operating frequency. The inductor of the on-die termination unit may be embodied by connecting a wire bonding, a package line pattern, a PCB line pattern, a wire line, and/or an inductor device to pads of the memory chip.

摘要翻译： 提供了具有电感器的存储器系统。 在存储器系统中，电感器连接到存储器芯片的片上终端单元，从而实现恒定的增益特性而不考虑工作频率的变化。 可以通过将引线接合，封装线图案，PCB线图案，有线线路和/或电感器件连接到存储器芯片的焊盘来实现片上端接单元的电感器。

公开(公告)号：US07420818B2

公开(公告)日：2008-09-02

申请号：US11368654

申请日：2006-03-06

申请人： Kwang-Soo Park ,  Jae-Jun Lee

发明人： Kwang-Soo Park ,  Jae-Jun Lee

IPC分类号： H05K1/18

CPC分类号： G11C5/063 ,  G11C7/1048

摘要： A memory module includes: one or more semiconductor memory devices; a plurality of module tabs configured to transmit and receive signals between the one or more semiconductor memory devices and external devices; a data bus configured to transfer signals between data input/output pins of the one or more semiconductor memory devices and the plurality of module tabs; and impedance-matching capacitive elements, each coupled between a line of the data bus and a reference voltage. Accordingly, the memory module and a memory system employing such a module can achieve improved impedance matching, thereby also improving signal integrity.

摘要翻译： 存储器模块包括：一个或多个半导体存储器件; 多个模块突出部，被配置为在所述一个或多个半导体存储器件和外部装置之间传送和接收信号; 数据总线，被配置为在所述一个或多个半导体存储器件的数据输入/输出引脚与所述多个模块标签之间传送信号; 和阻抗匹配电容元件，每个耦合在数据总线的一行与参考电压之间。 因此，采用这种模块的存储器模块和存储器系统可以实现改进的阻抗匹配，从而也提高信号完整性。

公开(公告)号：US20070205848A1

公开(公告)日：2007-09-06

申请号：US11649805

申请日：2007-01-05

申请人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

发明人： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

IPC分类号： H01P5/12 ,  H03H7/38

CPC分类号： H03H7/38

摘要： A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

摘要翻译： 终端电路连接到接收数据信号的输入缓冲器，并且包括连接到输入缓冲器以用于阻抗匹配的至少一个终端电阻器。 至少一个开关控制输入缓冲器与至少一个终端电阻器中相应的一个之间的连接。 控制信号发生器产生控制信号，用于通过控制至少一个开关中的每个开关来选择性地启用终端电路。 控制信号的输入周期小于或等于数据信号的输入周期。

公开(公告)号：US20070133247A1

公开(公告)日：2007-06-14

申请号：US11603648

申请日：2006-11-22

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。