公开(公告)号：US06725509B1

公开(公告)日：2004-04-27

申请号：US09634485

申请日：2000-08-08

申请人： Jae-ho Lee ,  Jong-hoon Lee

发明人： Jae-ho Lee ,  Jong-hoon Lee

IPC分类号： A44B1126

CPC分类号： A44B11/2523 ,  Y10T24/45665

摘要： Disclosed is a seat belt buckle. The seat belt buckle comprises a body frame; a release button slidably coupled to the body frame for unlatching a seat belt tongue from the seat belt buckle; a locking lever capable of being pivotally rotated about wings by a predetermined angle; a slider for supporting and fixing the locking lever; and an ejector for pushing the tongue in a longitudinal direction which is a lengthwise direction of the body frame. The body frame has an arch-shaped supporting beam which is integrally formed with the body frame in a manner such that the supporting beam is erected in a vertical direction. The supporting beam serves to limit movement of the slider and increase structural rigidity of the seat belt buckle. The slider has a width which is greater than that of the body frame and possesses shock-absorbing means for increasing durability of the seat belt buckle. The slider is formed with inclined projections. The release button has at least two release projections which are formed with inclined surfaces which are in turn brought into contact with the inclined projections of the slider.

摘要翻译： 公开了一种安全带扣。 座椅安全带扣包括主体框架; 释放按钮，其可滑动地联接到所述主体框架，用于从所述座椅安全带带扣解除座椅安全带舌片; 锁定杆，其能够围绕翼枢转预定角度; 用于支撑和固定锁定杆的滑块; 以及用于沿着身体框架的长度方向的纵向方向推动舌头的推出器。 主体框架具有拱形支撑梁，其与主体框架一体形成，使得支撑梁在竖直方向上竖立。 支撑梁用于限制滑块的移动并增加安全带扣的结构刚度。 该滑块的宽度大于车身框架的宽度，并且具有用于提高安全带带扣的耐久性的减震装置。 滑块形成有倾斜的突起。 释放按钮具有形成有倾斜表面的至少两个释放突起，所述倾斜表面又与滑块的倾斜突起接触。

公开(公告)号：US08477538B2

公开(公告)日：2013-07-02

申请号：US13170713

申请日：2011-06-28

申请人： Jong-hoon Lee ,  Jun-yong Park

发明人： Jong-hoon Lee ,  Jun-yong Park

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.

摘要翻译： 闪存器件包括包括多个存储器单元的存储单元阵列; 产生并输出位线电压控制信号的位线电压控制信号发生器; 以及通过多个位线连接到存储单元阵列的页面缓冲单元，并且响应于从位线电压控制信号发生器输出的位线电压控制信号来控制多个位线的电压电平，其中多个位线 位线包括与第一位线相邻的第一位线和第二位线，其中在位线预充电操作期间，第一位线处于程序禁止状态，第二位线处于编程中 状态，所述页缓冲器单元响应于所述位线电压控制信号而增加所述第一位线的电压电平，其中所述第一位线的电压电平的增加导致所述第二位线的电压电平增加，以及 其中所述位线电压控制信号的电压电平不受所述闪存器件的电源电压的变化的影响。

公开(公告)号：US06785211B2

公开(公告)日：2004-08-31

申请号：US09917267

申请日：2001-07-30

申请人： Jong-hoon Lee ,  Sung-ro Go ,  Kyoung-bok Jin ,  Ki-bong Yun

发明人： Jong-hoon Lee ,  Sung-ro Go ,  Kyoung-bok Jin ,  Ki-bong Yun

IPC分类号： G11B390

CPC分类号： G11B7/126

摘要： An automatic power control (APC) apparatus reducing time necessary for stabilizing an APC circuit at the initial stage of automatic power control of a disc drive is provided. The APC circuit is designed such that a voltage of a predetermined percent of an expected output voltage is previously added to an APC output voltage of the APC circuit of a laser diode, thereby greatly reducing a stabilizing time necessary for stabilizing an APC output voltage at an initial stage in a write or read mode. Therefore, the loss of data in a high speed write or read mode can be reduced. Particularly, the loss of data in a high speed write mode can be greatly reduced.

摘要翻译： 提供了一种自动功率控制（APC）装置，其减少在盘驱动器的自动功率控制的初始阶段稳定APC电路所需的时间。 APC电路被设计成使得预期输出电压的预定百分比的电压预先添加到激光二极管的APC电路的APC输出电压，从而大大减少了稳定APC输出电压所需的稳定时间 在写入或读取模式下的初始阶段。 因此，可以降低高速写入或读取模式下的数据丢失。 特别地，可以大大降低高速写入模式中的数据丢失。

公开(公告)号：US07385898B2

公开(公告)日：2008-06-10

申请号：US10624561

申请日：2003-07-23

申请人： Jong-hoon Lee ,  Gwang-ho Lee

发明人： Jong-hoon Lee ,  Gwang-ho Lee

IPC分类号： H04N5/783

CPC分类号： H04N5/85 ,  G11B27/105 ,  G11B27/19 ,  G11B27/24

摘要： An apparatus and a method determine an area of an optical disc in which an inner area and an outer area of the optical disc having an absolute time of 99 minutes are distinguished from each other by referring to a number of ATIP syncs. The method includes counting the number of ATIP syncs for one rotation of the optical disc at a current position of a pickup when ATIP information recorded on the optical disc indicates that the pickup is currently present in an area of the optical disk that is greater than or equal to 95 minutes; and determining the current position of the pickup by comparing the number of counted ATIP syncs with a reference number of ATIP syncs. Accordingly, time spent determining the area of an optical disc and accessing the optical disc is reduced.

摘要翻译： 一种装置和方法，通过参考ATIP同步数来确定其中具有绝对时间为99分钟的光盘的内部区域和外部区域彼此区分的光盘的区域。 该方法包括当记录在光盘上的ATIP信息指示拾取器当前存在于光盘的区域中时，对拾取器的当前位置处的光盘的一次旋转的ATIP同步的数量进行计数， 等于95分钟; 以及通过将计数的ATIP同步数与参考数量的ATIP同步进行比较来确定所述拾取器的当前位置。 因此，减少了确定光盘的面积和访问光盘的时间。

公开(公告)号：US06513747B1

公开(公告)日：2003-02-04

申请号：US09633971

申请日：2000-08-08

申请人： Jong-hoon Lee ,  Sung-woo Jin ,  Seung-man Kim

发明人： Jong-hoon Lee ,  Sung-woo Jin ,  Seung-man Kim

IPC分类号： B60R2236

CPC分类号： B60R22/4619 ,  B60R2022/1818 ,  B60R2022/468

摘要： A pretensioner comprises a pyrotechnic force generating device including a horizontal tube with a propellent charged cartridge, a housing receiving one end of the cylinder with the horizontal tube being supported to cooperate with the force generating device in order to reverse-rotate the reel; a force transmitting portion including an arm positioned in a first chamber of the housing, one end of which is directed to the piston in the cylinder and the other end of which is extended out of the cylinder, a pulley rotatably mounted on the other branched end of the arm and a cable fixed at one end to the housing, passed through the pulley, wound around the clutch disk and fixed at the other end to the clutch disk; and a pretensioner positioned in a second chamber, which comprises the clutch disk and a clutch portion, in which the clutch disk includes a circular groove formed around the periphery thereof to allow a length of the cable to be wound thereon, a plurality of second coupling projections each having a right-angled surface toward one direction and a slanted surface toward the other direction, at least three of coupling grooves cut out at one side in a right-angle and at the other side in a slant angle and a first fixing groove formed to fix the other end of the cable, and the clutch portion includes at least three of first coupling projections forming a slanted surface at one side and a right-angled surface at other side for cooperating with the coupling grooves and a plurality of third coupling projections or concaved grooves formed at the positions facing to the second coupling projections on one side surface of the reel.

摘要翻译： 预紧器包括烟火力产生装置，其包括具有推进剂充电药筒的水平管，容纳所述圆筒的一端的壳体，所述水平管被支撑以与所述力产生装置协作以使所述卷轴反向旋转; 力传递部分，其包括位于所述壳体的第一腔室中的臂，其一端被引导到所述气缸中的活塞并且另一端延伸出所述气缸;滑轮，可旋转地安装在所述另一分支端 并且一端固定在壳体上的电缆通过皮带轮，缠绕在离合器盘上，另一端固定在离合器盘上; 以及定位在第二室中的预紧器，所述预紧器包括所述离合器盘和离合器部分，所述离合器盘包括围绕其周边形成的圆形槽，以允许所述电缆的长度被缠绕在其上;多个第二联接器 每个具有朝向一个方向具有直角表面的突起和朝向另一个方向的倾斜表面，至少三个在直角的一侧切割的耦合槽和在倾斜角的另一侧切割的第一固定槽 形成为固定电缆的另一端，并且离合器部分包括在一侧形成倾斜表面的第一联接突起和在另一侧的直角表面中的至少三个，用于与联接槽配合，以及多个第三联接 在面向卷轴的一个侧表面上的第二联接突起的位置处形成的突起或凹槽。

公开(公告)号：US08593867B2

公开(公告)日：2013-11-26

申请号：US13155462

申请日：2011-06-08

申请人： Jong-hoon Lee ,  Nam-hee Lee

发明人： Jong-hoon Lee ,  Nam-hee Lee

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/26

摘要： A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell.

摘要翻译： 一种闪存装置，其中通过控制感测节点的电压和对应的读取方法来增加关闭单元余量，其中闪存装置包括存储单元阵列; 感测节点电压控制器，产生预充电电压和感测节点电压控制信号; 以及通过位线连接到存储单元阵列并具有页缓冲器的页缓冲器单元。 页缓冲器包括连接在相应位线和感测节点之间的位线连接单元，其根据感测节点电压控制信号来控制感测节点的电压; 预充电单元，其响应于预充电控制信号，根据预充电电压对感测节点进行预充电; 以及数据输入/输出单元，其响应于锁存控制信号感测感测节点的电压电平，并输出所选择的存储器单元的数据。

公开(公告)号：US20120020167A1

公开(公告)日：2012-01-26

申请号：US13170713

申请日：2011-06-28

申请人： Jong-hoon Lee ,  Jun-yong Park

发明人： Jong-hoon Lee ,  Jun-yong Park

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.

摘要翻译： 闪存器件包括包括多个存储器单元的存储单元阵列; 产生并输出位线电压控制信号的位线电压控制信号发生器; 以及通过多个位线连接到存储单元阵列的页面缓冲单元，并且响应于从位线电压控制信号发生器输出的位线电压控制信号来控制多个位线的电压电平，其中多个位线 位线包括与第一位线相邻的第一位线和第二位线，其中在位线预充电操作期间，第一位线处于程序禁止状态，第二位线处于编程中 状态，所述页缓冲器单元响应于所述位线电压控制信号而增加所述第一位线的电压电平，其中所述第一位线的电压电平的增加导致所述第二位线的电压电平增加，以及 其中所述位线电压控制信号的电压电平不受所述闪存器件的电源电压的变化的影响。

公开(公告)号：US20110305087A1

公开(公告)日：2011-12-15

申请号：US13155462

申请日：2011-06-08

申请人： Jong-hoon Lee ,  Nam-hee Lee

发明人： Jong-hoon Lee ,  Nam-hee Lee

IPC分类号： G11C16/04 ,  G11C16/26

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/26

摘要： A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell.

摘要翻译： 一种闪存装置，其中通过控制感测节点的电压和对应的读取方法来增加关闭单元余量，其中闪存装置包括存储单元阵列; 感测节点电压控制器，产生预充电电压和感测节点电压控制信号; 以及通过位线连接到存储单元阵列并具有页缓冲器的页缓冲器单元。 页缓冲器包括连接在相应位线和感测节点之间的位线连接单元，其根据感测节点电压控制信号来控制感测节点的电压; 预充电单元，其响应于预充电控制信号，根据预充电电压对感测节点进行预充电; 以及数据输入/输出单元，其响应于锁存控制信号感测感测节点的电压电平，并输出所选择的存储器单元的数据。

公开(公告)号：US07916601B2

公开(公告)日：2011-03-29

申请号：US12285564

申请日：2008-10-08

申请人： Joo-youp Kim ,  Seung-bum Lee ,  Jong-hoon Lee ,  Sung-yong Chung

发明人： Joo-youp Kim ,  Seung-bum Lee ,  Jong-hoon Lee ,  Sung-yong Chung

IPC分类号： G11B7/00

CPC分类号： G11B20/10481 ,  G11B7/0062 ,  G11B7/1267 ,  G11B20/10009

摘要： A write strategy method, medium, and apparatus. The method includes writing a signal to a storage medium by using a predetermined power and an initial write strategy, calculating variation characteristics of a data signal which separately correspond to variations of write strategy parameters, if the written signal does not satisfy initial quality standards, and calculating correlations among periods of the data signal and correlations among the write strategy parameters by using the variation characteristics of the data signal, and determining the write strategy parameters based on the correlations among the periods of the data signal and the correlations among the write strategy parameters.

摘要翻译： 写策略方法，媒体和装置。 该方法包括：如果写入信号不满足初始质量标准，则通过使用预定功率和初始写入策略将信号写入存储介质，计算分别对应于写入策略参数的变化的数据信号的变化特性，以及 通过使用数据信号的变化特性来计算数据信号的周期和写入策略参数之间的相关性，并且基于数据信号的周期与写入策略参数之间的相关性之间的相关性来确定写入策略参数 。

公开(公告)号：US20090092016A1

公开(公告)日：2009-04-09

申请号：US12285564

申请日：2008-10-08

申请人： Joo-youp Kim ,  Seung-bum Lee ,  Jong-hoon Lee ,  Sung-yong Chung

发明人： Joo-youp Kim ,  Seung-bum Lee ,  Jong-hoon Lee ,  Sung-yong Chung

IPC分类号： G11B7/00

CPC分类号： G11B20/10481 ,  G11B7/0062 ,  G11B7/1267 ,  G11B20/10009

摘要： A write strategy method, medium, and apparatus. The method includes writing a signal to a storage medium by using a predetermined power and an initial write strategy, calculating variation characteristics of a data signal which separately correspond to variations of write strategy parameters, if the written signal does not satisfy initial quality standards, and calculating correlations among periods of the data signal and correlations among the write strategy parameters by using the variation characteristics of the data signal, and determining the write strategy parameters based on the correlations among the periods of the data signal and the correlations among the write strategy parameters.

摘要翻译： 写策略方法，媒体和装置。 该方法包括：如果写入信号不满足初始质量标准，则通过使用预定功率和初始写入策略将信号写入存储介质，计算分别对应写入策略参数的变化的数据信号的变化特性，以及 通过使用数据信号的变化特性来计算数据信号的周期和写入策略参数之间的相关性，并且基于数据信号的周期与写入策略参数之间的相关性之间的相关性来确定写入策略参数 。