公开(公告)号：US07838375B1

公开(公告)日：2010-11-23

申请号：US11807215

申请日：2007-05-25

申请人： Mingwei Xu ,  Jamal Ramdani

发明人： Mingwei Xu ,  Jamal Ramdani

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： A system and method are disclosed for providing an improved polyemit module for a self aligned heterojunction bipolar transistor architecture. The polyemit module of the transistor of the present invention is formed using a double layer deposition process. In the double layer deposition process, the first layer is a layer of emitter polysilicon and the second layer is a sacrificial layer of silicon germanium (SiGe). The shape and thickness of the emitter polysilicon layer of the polyemit module provides (1) a reduction in the overall resistance of the emitter and (2) an increase in the contact area between the emitter polysilicon layer and a contact structure that is more than three times the contact area that is provided in prior art polyemit modules.

摘要翻译： 公开了一种用于为自对准异质结双极晶体管结构提供改进的聚合模块的系统和方法。 本发明的晶体管的聚合模块使用双层沉积工艺形成。 在双层沉积工艺中，第一层是发射极多晶硅层，第二层是硅锗牺牲层（SiGe）。 多模块模块的发射极多晶硅层的形状和厚度提供了（1）发射极整体电阻的降低和（2）发射极多晶硅层和接触结构之间的接触面积的增加，该接触面积大于三 倍于现有技术聚合模块中提供的接触面积。

公开(公告)号：US07846806B1

公开(公告)日：2010-12-07

申请号：US11807216

申请日：2007-05-25

申请人： Jamal Ramdani ,  Mingwei Xu

发明人： Jamal Ramdani ,  Mingwei Xu

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/7378 ,  H01L29/0817 ,  H01L29/66242

摘要： A system and method are disclosed for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture. The transistor of the present invention comprises a non-selective epitaxial growth (NSEG) collector, an NSEG base, an NSEG emitter and a raised external base that is formed by the selective epitaxial growth (SEG) of a doped polysilicon layer.

摘要翻译： 公开了一种用于使用台面发射极 - 基础结构提供自对准硅锗（SiGe）异质结双极晶体管的系统和方法。 本发明的晶体管包括通过掺杂多晶硅层的选择性外延生长（SEG）形成的非选择性外延生长（NSEG）集电极，NSEG基极，NSEG发射极和隆起的外部基极。

公开(公告)号：US07566626B1

公开(公告)日：2009-07-28

申请号：US11805417

申请日：2007-05-23

申请人： Mingwei Xu ,  Jamal Ramdani

发明人： Mingwei Xu ,  Jamal Ramdani

IPC分类号： H01L21/331

CPC分类号： H01L29/66272 ,  H01L21/02532 ,  H01L21/02639

摘要： A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a polysilicon external raised base. Then an emitter window is etched through the polysilicon external raised base down to the top layer of silicon oxide. A wet etch process is performed to form a cavity in the at least two layers of silicon oxide. Different wet etch rates of the silicon layers with respect to the wet etch process cause the cavity to be formed with a shape that optimizes selective epitaxial growth in the cavity. Polysilicon rich corners and a monocrystalline silicon base are then formed within the cavity.

摘要翻译： 公开了一种系统和方法，用于使用改进的空腔形成来提供完全自对准的双极晶体管，以优化选择性外延生长。 形成晶体管的集电极，并且在集电极上方形成至少两层氧化硅，并被多晶硅外部凸起的基底覆盖。 然后通过多晶硅外部凸起基底向下蚀刻发射器窗口，直到氧化硅的顶层。 执行湿蚀刻工艺以在至少两层氧化硅中形成空腔。 相对于湿蚀刻工艺，硅层的不同的湿蚀刻速率导致空腔形成为优化空腔中的选择性外延生长的形状。 然后在腔内形成富含多晶硅的拐角和单晶硅基底。

公开(公告)号：US08723296B2

公开(公告)日：2014-05-13

申请号：US12927947

申请日：2010-11-30

申请人： Jamal Ramdani

发明人： Jamal Ramdani

IPC分类号： H01L29/66 ,  H01L21/20

CPC分类号： H01L21/0254 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02639 ,  H01L29/2003

摘要： A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.

摘要翻译： 一种方法包括在衬底上形成应力补偿堆叠，其中应力补偿堆叠在衬底上具有压应力。 该方法还包括在衬底上形成一个或多个III族氮化物岛，其中一个或多个III族氮化物岛在衬底上具有拉伸应力。 该方法还包括使用来自应力补偿叠层的压缩应力至少部分地抵消来自一个或多个III族氮化物岛的拉伸应力。 形成应力补偿堆叠可以包括在衬底上形成一个或多个氧化物层和一个或多个氮化物层。 一个或多个氧化物层可以具有压应力，一个或多个氮化物层可以具有拉伸应力，并且氧化物和氮化物层可以共同地具有压应力。 可以选择氧化物层和氮化物层的厚度以提供所需量的应力补偿。

公开(公告)号：US20140077266A1

公开(公告)日：2014-03-20

申请号：US13617584

申请日：2012-09-14

申请人： Jamal Ramdani ,  Michael Murphy ,  Linlin Liu

发明人： Jamal Ramdani ,  Michael Murphy ,  Linlin Liu

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/778 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

摘要翻译： 异质结构半导体器件包括设置在第一有源层上的第一有源层和第二有源层。 在第一和第二有源层之间形成二维电子气层。 第一栅介质层设置在第二有源层上。 第二栅极电介质层设置在第一栅极电介质层上。 钝化层设置在第二栅极电介质层上。 栅极延伸穿过钝化层到第二栅极介电层。 第一和第二欧姆触点电连接到第二有源层。 第一和第二欧姆触点横向间隔开，栅极设置在第一和第二欧姆触点之间。

公开(公告)号：US08591427B2

公开(公告)日：2013-11-26

申请号：US12927204

申请日：2010-11-09

申请人： Lawrence H. Zuckerman ,  Michael X. Maida ,  Dennis M. Monticelli ,  James B. Wieser ,  Jamal Ramdani ,  Paul Mawson ,  Moulay Mohamed Ibourk

发明人： Lawrence H. Zuckerman ,  Michael X. Maida ,  Dennis M. Monticelli ,  James B. Wieser ,  Jamal Ramdani ,  Paul Mawson ,  Moulay Mohamed Ibourk

IPC分类号： A61B5/02

CPC分类号： A61B5/04007 ,  A61B5/7239 ,  A61B5/743

摘要： A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.

摘要翻译： 一种系统包括配置成测量第一和第二磁场的至少一个第一磁场传感器。 该系统还包括至少一个第二磁场传感器，其配置成基本上不测量第一磁场来测量第二磁场。 该系统还包括配置成执行信号消除以产生第一磁场的测量并且基于第一磁场的测量产生输出的处理电路。 传感器可以代表磁电传感器。 磁电传感器可以被配置为将与第一和/或第二磁场相关联的电信号上变频到更高的频率。 处理电路可以被配置为识别与患者心脏相关联的一个或多个问题。

公开(公告)号：US08581579B2

公开(公告)日：2013-11-12

申请号：US12927205

申请日：2010-11-09

申请人： Lawrence H. Zuckerman ,  Michael X. Maida ,  Dennis M. Monticelli ,  James B. Wieser ,  Jamal Ramdani

发明人： Lawrence H. Zuckerman ,  Michael X. Maida ,  Dennis M. Monticelli ,  James B. Wieser ,  Jamal Ramdani

IPC分类号： G01R33/12

CPC分类号： A61B5/04007 ,  A61B5/7239 ,  A61B5/743

摘要： A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field. The chopping could involve intermittently shielding the magnetic field sensor from the magnetic field or moving the magnetic field sensor with respect to the magnetic field.

摘要翻译： 一种方法包括使用具有交替的磁致伸缩材料层和压电材料的磁场传感器来产生表示磁场的电信号。 该方法还包括执行上变频或下变频，使得表示磁场的电信号具有比磁场频率更高或更低的频率。 在磁场转换成电信号之前执行上转换或下变频。 上转换或下转换可以通过使磁场传感器反复敏感和脱敏来进行。 这可以使用永磁体和电磁体，没有永磁体的电磁体或可动永磁体来完成。 也可以通过切割磁场来执行上变频或下变频。 斩波可能会将磁场传感器与磁场间断地屏蔽或相对于磁场移动磁场传感器。

公开(公告)号：US08377788B2

公开(公告)日：2013-02-19

申请号：US12946305

申请日：2010-11-15

申请人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

发明人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/7371

摘要： A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.

摘要翻译： 通过蚀刻外延形成的结构来形成SiGe异质结双极晶体管，以形成具有位于其间的集电极区域，帽区域和缺口SiGe基极区域的台面。 在SiGe基极区域的凹口中形成保护塞，使得可以在集电区域和盖区域的侧面上形成厚的非导电区域。 一旦形成了非导电区域，就去除了保护塞。 然后形成外部碱基以位于凹口中并且接触基极区域，随后形成隔离区域和发射极区域。

公开(公告)号：US20110180854A1

公开(公告)日：2011-07-28

申请号：US12657757

申请日：2010-01-27

申请人： Jamal Ramdani

发明人： Jamal Ramdani

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/225 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.

摘要翻译： 一种方法包括在半导体器件中形成松弛层。 该方法还包括在松弛层上形成拉伸层，其中拉伸层具有拉伸应力。 该方法还包括在松弛层上形成压缩层，其中压缩层具有压应力。 压缩层具有大致等于或大于松弛，拉伸和压缩层中的自发极化的压电极化。 压缩层中的压电极化可能与压缩层中的自发极化方向相反。 松弛层可以包括氮化镓，拉伸层可以包括氮化镓铝，并且压缩层可以包括铝铟镓氮。

公开(公告)号：US20110042778A1

公开(公告)日：2011-02-24

申请号：US12917332

申请日：2010-11-01

申请人： Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

发明人： Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

IPC分类号： H01L29/06

CPC分类号： H01L27/1207 ,  H01L21/76264

摘要： One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.

摘要翻译： 可以在半导体衬底的第一部分周围形成一个或多个沟槽，并且可以在半导体衬底的第一部分之下形成绝缘层。 一个或多个沟槽和绝缘层将衬底的第一部分与衬底的第二部分电隔离。 可以通过在硅衬底中的诸如硅锗层的衬底中形成掩埋层来形成绝缘层。 可以形成通过衬底到掩埋层的一个或多个第一沟槽，并且可以在掩埋层中形成开放空间（例如通过使用对硅上的硅锗的选择性蚀刻）。 一个或多个第一沟槽和开放空间可以可选地用绝缘材料填充。 可以形成并填充一个或多个第二沟槽以隔离衬底的第一部分。