公开(公告)号：US08377788B2

公开(公告)日：2013-02-19

申请号：US12946305

申请日：2010-11-15

申请人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

发明人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/7371

摘要： A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.

摘要翻译： 通过蚀刻外延形成的结构来形成SiGe异质结双极晶体管，以形成具有位于其间的集电极区域，帽区域和缺口SiGe基极区域的台面。 在SiGe基极区域的凹口中形成保护塞，使得可以在集电区域和盖区域的侧面上形成厚的非导电区域。 一旦形成了非导电区域，就去除了保护塞。 然后形成外部碱基以位于凹口中并且接触基极区域，随后形成隔离区域和发射极区域。

公开(公告)号：US20120119262A1

公开(公告)日：2012-05-17

申请号：US12946305

申请日：2010-11-15

申请人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

发明人： Wibo Van Noort ,  Jamal Ramdani ,  Andre Labonte ,  Donald Robertson Getchell

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/7371

摘要： A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.

摘要翻译： 通过蚀刻外延形成的结构来形成SiGe异质结双极晶体管，以形成具有位于其间的集电极区域，帽区域和缺口SiGe基极区域的台面。 在SiGe基极区域的凹口中形成保护塞，使得可以在集电区域和盖区域的侧面上形成厚的非导电区域。 一旦形成了非导电区域，就去除了保护塞。 然后形成外部碱基以位于凹口中并且接触基极区域，随后形成隔离区域和发射极区域。

公开(公告)号：US20090203184A1

公开(公告)日：2009-08-13

申请号：US11574013

申请日：2005-08-19

申请人： Peter Magnee ,  Wibo Van Noort ,  Johannes Donkers

发明人： Peter Magnee ,  Wibo Van Noort ,  Johannes Donkers

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/8249

摘要： The illumination system has a light source (1) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator (2) for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis (25) of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector (3) at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser (17). The illumination system emits light with a uniform spatial and spatio-angular color distribution.

摘要翻译： 照明系统具有具有多个发光体（R，G，B）的光源（1）。 光发射体至少包括第一原色的第一发光二极管和第二原色的至少第二发光二极管，第一和第二原色彼此不同。 照明系统具有用于准直由发光体发射的光的分面光准直器（2）。 分面光学增白器沿照明系统的纵向轴线（25）布置。 在分面光准直仪中的光传播基于全内反射或基于设置在刻面光准直仪的面上的反射涂层的反射。 分面光准直器在远离光源的一侧融合成分面的光反射器（3）。 照明系统还包括光成形漫射器（17）。 照明系统以均匀的空间和空间角色彩分布发光。

公开(公告)号：US20080258182A1

公开(公告)日：2008-10-23

申请号：US11577311

申请日：2005-10-13

申请人： Prabhat Agarwal ,  Jan W. Slotboom ,  Wibo Van Noort

发明人： Prabhat Agarwal ,  Jan W. Slotboom ,  Wibo Van Noort

IPC分类号： H01L29/808 ,  H01L21/8232 ,  H01L21/337

CPC分类号： H01L27/098 ,  H01L21/8248 ,  H01L27/0623

摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.

摘要翻译： 一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层 双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。 结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

公开(公告)号：US07883954B2

公开(公告)日：2011-02-08

申请号：US11574013

申请日：2005-08-19

申请人： Peter Magnee ,  Wibo Van Noort ,  Johannes Donkers

发明人： Peter Magnee ,  Wibo Van Noort ,  Johannes Donkers

IPC分类号： H01L21/8238

CPC分类号： H01L29/66242 ,  H01L21/8249

摘要： The illumination system has a light source (1) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator (2) for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis (25) of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector (3) at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser (17). The illumination system emits light with a uniform spatial and spatio-angular color distribution.

摘要翻译： 照明系统具有具有多个发光体（R，G，B）的光源（1）。 光发射体至少包括第一原色的第一发光二极管和第二原色的至少第二发光二极管，第一和第二原色彼此不同。 照明系统具有用于准直由发光体发射的光的分面光准直器（2）。 分面光学增白器沿照明系统的纵向轴线（25）布置。 在分面光准直仪中的光传播基于全内反射或基于设置在刻面光准直仪的面上的反射涂层的反射。 分面光准直器在远离光源的一侧融合成分面的光反射器（3）。 照明系统还包括光成形漫射器（17）。 照明系统以均匀的空间和空间角色彩分布发光。

公开(公告)号：US07989875B2

公开(公告)日：2011-08-02

申请号：US12277102

申请日：2008-11-24

申请人： Wibo Van Noort ,  Theodore James Letavic ,  Francis Zaato ,  Charudatta Mandhare

发明人： Wibo Van Noort ,  Theodore James Letavic ,  Francis Zaato ,  Charudatta Mandhare

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/0623 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546 ,  H01L27/11558

摘要： A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.

摘要翻译： BiCMOS衬底包括具有掩埋载流子层的双极区域和延伸到掩埋载体层中的深沟槽隔离（DTI）沟槽，以在DTI沟槽内的掩埋阱注入之上形成表面阱注入，埋置阱注入为 掩埋载体层部分在DTI沟槽内。 浮动栅极设置在载体上。 可选地，高压控制栅极由掩埋阱注入的堆叠和DTI沟槽内的表面阱注入形成。 任选地，由双极工艺基底多晶层形成的多晶硅层设置在浮动栅极上。 可选地，在衬底上形成浅阱隔离区域，在浅阱区域上设置浮置栅极，并且在浮置栅极上方设置由双极性工艺基底多晶硅形成的覆盖控制栅极。

公开(公告)号：US20060131736A1

公开(公告)日：2006-06-22

申请号：US10560004

申请日：2004-06-08

申请人： Andreas Jansman ,  Ronald Dekker ,  Godefridus Hurkx ,  Wibo Van Noort ,  Antonius Lucien Kemmeren

发明人： Andreas Jansman ,  Ronald Dekker ,  Godefridus Hurkx ,  Wibo Van Noort ,  Antonius Lucien Kemmeren

IPC分类号： H01L23/34

CPC分类号： H01L24/82 ,  H01L23/36 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/24 ,  H01L2223/6644 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

摘要： The electronic device comprises a substrate (1) with a cavity (6) in which an active device (8) is present. On the first side (2) of the substrate an interconnect structure (17) extends over the cavity and the substrate. On the second side (3) of the substrate to which the cavity extends, a heat sink (23) is available. The device is particularly suitable for use at high frequencies, for instance higher than 2 GHz and under conditions of high dissipation.

摘要翻译： 电子设备包括具有空腔（6）的衬底（1），其中存在有源器件（8）。 在衬底的第一侧（2）上，互连结构（17）在空腔和衬底上延伸。 在空腔延伸的基板的第二面（3）上，散热片（23）是可用的。 该器件特别适用于高频率，例如高于2GHz和高耗散条件下使用。

公开(公告)号：US08373236B2

公开(公告)日：2013-02-12

申请号：US12304506

申请日：2007-06-12

申请人： Erwin Hijzen ,  Joost Melai ,  Wibo Van Noort ,  Johannes Donkers ,  Philippe Meunier-Beillard ,  Andreas M. Piontek ,  Li Jen Choi ,  Stefaan Van Huylenbroeck

发明人： Erwin Hijzen ,  Joost Melai ,  Wibo Van Noort ,  Johannes Donkers ,  Philippe Meunier-Beillard ,  Andreas M. Piontek ,  Li Jen Choi ,  Stefaan Van Huylenbroeck

IPC分类号： H01L27/06

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7378

摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

摘要翻译： 本发明涉及具有基板（11）和半导体本体（1）的半导体器件（10），该半导体器件（1）包括双极晶体管，依次具有集电极区域（2），基极区域（3）和发射极区域 4），其中半导体主体包括包括集电极区域（2）和基极区域（3）的至少一部分的突出台面（5），该台面由隔离区域（6）包围。 根据本发明，半导体器件（10）还包括具有源极区域，漏极区域，插入沟道区域，叠加栅极电介质（7）和栅极区域（8）的场效应晶体管，该栅极区域 （8）形成场效应晶体管的最高部分，台面（5）的高度大于栅极区域（8）的高度。 该装置可以通过根据本发明的方法廉价且容易地制造，并且双极晶体管可以具有优异的高频特性。

公开(公告)号：US20070197043A1

公开(公告)日：2007-08-23

申请号：US10599032

申请日：2005-03-11

申请人： Wibo Van Noort ,  Eyup Aksen

发明人： Wibo Van Noort ,  Eyup Aksen

IPC分类号： H01L21/31

CPC分类号： H01L21/76229 ,  H01L21/02002

摘要： The invention relates to a method of manufacturing a semiconductor device comprising a substrate (1) and a semiconductor body (2) in which at least one semiconductor element is formed, wherein, in the semiconductor body (2), a semiconductor island (3) is formed by forming a first cavity (4) in the surface of the semiconductor body (2), the walls of said first cavity being covered with a first dielectric layer (6), after which, by means of underetching through the bottom of the cavity (4), a lateral part of the semiconductor body (2) is removed, thereby forming a cavity (20) in the semiconductor body (2) above which the semiconductor island (3) is formed, and wherein a second cavity (5) is formed in the surface of the semiconductor body (2), the walls of said second cavity being covered with a second dielectric layer, and one of the walls covered with said second dielectric layer forming a side wall of the semiconductor island (3). According to the invention, the same dielectric layer (6) is chosen for the first and the second dielectric layer, a lateral size of the second cavity (5) and the thickness of the dielectric layer (6) are chosen such that the second cavity (5) becomes nearly completely filled by the dielectric layer (6), and the lateral sizes of the first cavity (4) are chosen such that the walls and the bottom of the first cavity (4) are provided with a uniform coating by the dielectric layer (6). In this way, a semiconductor island (3) which is isolated from its environment can be made using a minimum number of (masking) steps.

摘要翻译： 本发明涉及一种制造半导体器件的方法，该半导体器件包括其中形成有至少一个半导体元件的衬底（1）和半导体本体（2），其中在半导体本体（2）中，半导体岛（3） 通过在半导体本体（2）的表面中形成第一空腔（4）形成，所述第一腔的壁被第一介电层（6）覆盖，之后借助于穿过半导体本体 空腔（4），半导体主体（2）的侧面部分被去除，从而在半导体主体（2）中形成空腔（20），在半导体主体（2）之上形成半导体岛（3），并且其中第二腔 ）形成在半导体本体（2）的表面中，所述第二腔的壁被第二电介质层覆盖，并且覆盖有形成半导体岛（3）的侧壁的所述第二电介质层的一个壁， 。 根据本发明，为第一和第二介电层选择相同的介电层（6），第二腔（5）的横向尺寸和电介质层（6）的厚度被选择为使得第二腔 （5）变得几乎完全被电介质层（6）填充，并且第一空腔（4）的横向尺寸被选择为使得第一空腔（4）的壁和底部被均匀地涂覆 电介质层（6）。 以这种方式，可以使用最少数量（掩蔽）步骤来制造与其环境隔离的半导体岛（3）。

公开(公告)号：US20060163692A1

公开(公告)日：2006-07-27

申请号：US10564582

申请日：2004-07-15

申请人： Celine Detecheverry ,  Wibo Van Noort

发明人： Celine Detecheverry ,  Wibo Van Noort

IPC分类号： H01L29/00

CPC分类号： H01L23/5222 ,  H01F2017/008 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.

摘要翻译： 本发明提供一种包括多个层的半导体器件，所述半导体器件包括： - 具有第一主表面的衬底， - 在所述衬底的第一主表面上制造的电感元件，所述电感元件包括至少一个导线 以及 - 至少一层中的多个耕作结构，其中所述多个耕作结构电连接在一起并且被布置成几何图案，以便基本上禁止通过所述耕作结构中的电流来诱导所述耕作结构中的图像电流 电感元件。 上述半导体器件的优点是，通过使用这种耕作结构，获得了具有改善的品质因数的电感元件。 本发明还提供一种在包括多个层的半导体器件中提供电感元件的方法。