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14 条记录 (耗时 0.02 秒)

    Mitigating silent data corruption in a buffered memory module architecture
    2.
    发明申请
    Mitigating silent data corruption in a buffered memory module architecture 失效
    减轻缓冲内存模块架构中的无声数据损坏

    公开(公告)号：US20070011562A1

    公开(公告)日：2007-01-11

    申请号：US11165693

    申请日：2005-06-24

    申请人： James Alexander ,  Suresh Chittor ,  Dennis Brzezinski ,  Kai Cheng

    发明人： James Alexander ,  Suresh Chittor ,  Dennis Brzezinski ,  Kai Cheng

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1004 ,  H03M13/09 ,  H03M13/19

    摘要： Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

    摘要翻译： 本发明的实施例一般涉及用于减轻完全缓冲存储器模块架构中的无声数据损坏的系统，装置和方法。 在一个实施例中，存储器控制器包括具有M位CRC和N位CRC的存储器通道位通道误差检测器，其中N小于M.如果至少一个位线 内存通道失败。 在一个实施例中，如果至少一个位通道已经失败，则存储器控制器选择性地将纠错码（ECC）的强错误检测能力与N位CRC结合起来，以指示重新发送故障数据的需要。 描述和要求保护其他实施例。

    Mitigating silent data corruption in a buffered memory module architecture
    3.
    发明授权
    Mitigating silent data corruption in a buffered memory module architecture 失效
    减轻缓冲内存模块架构中的无声数据损坏

    公开(公告)号：US07734980B2

    公开(公告)日：2010-06-08

    申请号：US11165693

    申请日：2005-06-24

    申请人： James W. Alexander ,  Suresh Chittor ,  Dennis W. Brzezinski ,  Kai Cheng ,  Rajat Agarwal

    发明人： James W. Alexander ,  Suresh Chittor ,  Dennis W. Brzezinski ,  Kai Cheng ,  Rajat Agarwal

    IPC分类号： H03M13/00 ,  G11C29/00

    CPC分类号： G06F11/1004 ,  H03M13/09 ,  H03M13/19

    摘要： Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

    摘要翻译： 本发明的实施例一般涉及用于减轻完全缓冲存储器模块架构中的无声数据损坏的系统，装置和方法。 在一个实施例中，存储器控制器包括具有M位CRC和N位CRC的存储器通道位通道误差检测器，其中N小于M.如果至少一个位线 内存通道失败。 在一个实施例中，如果至少一个位通道已经失败，则存储器控制器选择性地将纠错码（ECC）的强错误检测能力与N位CRC结合起来，以指示重新发送故障数据的需要。 描述和要求保护其他实施例。

    Selective conflict write flush
    6.
    发明授权
    Selective conflict write flush 失效
    选择性冲突写入齐平

    公开(公告)号：US6145062A

    公开(公告)日：2000-11-07

    申请号：US13775

    申请日：1998-01-26

    申请人： Suresh Chittor ,  Suneeta Sah ,  Prantik Kumar Nag ,  Joseph Ku

    发明人： Suresh Chittor ,  Suneeta Sah ,  Prantik Kumar Nag ,  Joseph Ku

    IPC分类号： G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/1631

    摘要： A method and apparatus of selectively flushing a conflicted write transaction from a memory controller. According to the method, a new transaction is received that identifies a memory address to which the transaction is directed. It is determined whether an address of the new transaction matches an address of any previously queued transaction. When a match occurs, the one previously queued transaction that matches the new transaction is flushed from queue.

    摘要翻译： 一种从存储器控制器选择性地刷新冲突的写事务的方法和装置。 根据该方法，接收到新的事务，其识别事务所针对的存储器地址。 确定新事务的地址是否匹配任何先前排队的事务的地址。 当发生匹配时，与新事务匹配的先前排队的事务将从队列中刷新。

    Coherent variable length reads from system memory
    8.
    发明授权
    Coherent variable length reads from system memory 失效
    相干可变长度读取系统内存

    公开(公告)号：US06298420B1

    公开(公告)日：2001-10-02

    申请号：US09567139

    申请日：2000-05-08

    申请人： Suresh Chittor ,  Chih-Cheh Chen ,  Sin Sim Tan ,  Jonathan Nick Spitz

    发明人： Suresh Chittor ,  Chih-Cheh Chen ,  Sin Sim Tan ,  Jonathan Nick Spitz

    IPC分类号： G06F1202

    CPC分类号： G06F12/0831 ,  G06F12/0886 ,  G06F13/1642

    摘要： Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

    摘要翻译： 当存储器控制器连接到流水线总线和串行总线时，用于在存储器控制器中处理串行总线读请求的方法和装置。 根据该方法，读取请求消息被接收并被分割成几个原子事务。 原子交易是在流水线上发行的。 与几个原子事务相关的数据存储在队列中。 请求的数据从队列中读取并放在串行总线上的响应消息中。

    Bus protocol for atomic transactions
    9.
    发明授权
    Bus protocol for atomic transactions 失效
    总线协议原子交易

    公开(公告)号：US5987552A

    公开(公告)日：1999-11-16

    申请号：US013774

    申请日：1998-01-26

    申请人： Suresh Chittor ,  Suvansh Kapur ,  Lily Looi

    发明人： Suresh Chittor ,  Suvansh Kapur ,  Lily Looi

    IPC分类号： G06F13/38 ,  G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/387

    摘要： A method for processing an atomic transaction in a multi-bus system that includes a local bus and a remote bus. According to the method, a first transaction in an atomic sequence is received from the local bus. The first transaction is terminated on the local bus. The first transaction is performed on the remote bus. A response to the first transaction is received and the response is placed on the local bus.

    摘要翻译： 一种用于在包括本地总线和远程总线的多总线系统中处理原子事务的方法。 根据该方法，从本地总线接收原子序列中的第一事务。 第一笔交易在本地公车上终止。 第一个事务在远程总线上执行。 接收到对第一个事务的响应，并将响应放在本地总线上。