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公开(公告)号：US5158898A
公开(公告)日：1992-10-27
申请号：US794279
申请日：1991-11-19
申请人： James D. Hayden , Bich-Yen Nguyen , Kent J. Cooper
发明人： James D. Hayden , Bich-Yen Nguyen , Kent J. Cooper
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/84 , H01L29/78678
摘要： A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).
摘要翻译： 一种自对准的下栅极TFT器件（10）。 形成基层（14）。 形成在基底层（14）上方的导电层（16）。 形成在导电层（16）上方的电介质层（18）。 形成覆盖在电介质层（18）上的牺牲层（20）。 层（16,18和20）被蚀刻以形成“柱”区域。 将覆盖在“柱”区域上的电介质层（22）和平面层（24）被回蚀刻以形成基本上平坦的表面并且暴露牺牲层（20）的顶部部分。 去除牺牲层（20），并且形成覆盖导电区域（16）和平面层（22）的导电层（28）。 导电层（28）用于通过形成邻近对准的插塞区域（32）的源区（33）和漏区（34）来形成自对准TFT器件（10）。
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公开(公告)号：US5567958A
公开(公告)日：1996-10-22
申请号：US452944
申请日：1995-05-31
IPC分类号： H01L21/336 , H01L27/11 , H01L29/786 , H01L29/78
CPC分类号： H01L27/1108 , H01L29/66757 , H01L29/78696 , Y10S257/903
摘要： A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.
摘要翻译： 薄膜晶体管和SRAM存储单元包括由开口（22）和上覆绝缘层（11）分开的薄膜源区和漏区（12,14）。 薄膜通道层（16）覆盖薄膜源区和漏区（12,14），绝缘层（11）的一部分由开口（22）露出。 薄膜栅电极（20）位于开口（22）中并且在薄膜通道层（16）中限定薄膜通道区（24）。 薄膜栅电极（20）通过栅介质层（18）与薄膜沟道区（24）分离。 薄膜通道区域（24）沿薄膜源极和漏极区域（12,14）的垂直壁表面（26,28）延伸，为薄膜晶体管提供延长的沟道长度。
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公开(公告)号：US5543635A
公开(公告)日：1996-08-06
申请号：US455268
申请日：1995-05-31
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/76 , H01L29/04 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78618 , H01L29/78624 , H01L29/78678 , Y10S148/109
摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。
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公开(公告)号：US5262352A
公开(公告)日：1993-11-16
申请号：US937025
申请日：1992-08-31
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76834 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).
摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。
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公开(公告)号：US5510278A
公开(公告)日：1996-04-23
申请号：US300770
申请日：1994-09-06
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L21/786
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78618 , H01L29/78624 , H01L29/78678 , Y10S148/109
摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。
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公开(公告)号：US5408130A
公开(公告)日：1995-04-18
申请号：US286592
申请日：1994-08-05
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/48 , H01L29/46 , H01L29/62
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76834 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).
摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。
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7.发明授权
公开(公告)号：US5235189A
公开(公告)日：1993-08-10
申请号：US923649
申请日：1992-08-03
申请人： James D. Hayden , Bich-Yen Nguyen , Cooper Kent J.
发明人： James D. Hayden , Bich-Yen Nguyen , Cooper Kent J.
IPC分类号： H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/84 , H01L29/78678
摘要： A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).
摘要翻译： 一种自对准的下栅极TFT器件（10）。 形成基层（14）。 形成在基底层（14）上方的导电层（16）。 形成在导电层（16）上方的电介质层（18）。 形成覆盖在电介质层（18）上的牺牲层（20）。 层（16,18和20）被蚀刻以形成“柱”区域。 将覆盖在“柱”区域上的电介质层（22）和平面层（24）被回蚀刻以形成基本上平坦的表面并且暴露牺牲层（20）的顶部部分。 去除牺牲层（20），并且形成覆盖导电区域（16）和平面层（22）的导电层（28）。 导电层（28）用于通过形成邻近对准的插塞区域（32）的源区（33）和漏区（34）来形成自对准TFT器件（10）。
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公开(公告)号：US5308997A
公开(公告)日：1994-05-03
申请号：US902216
申请日：1992-06-22
IPC分类号： H01L29/78 , H01L21/336 , H01L27/11 , H01L29/417 , H01L29/786 , H01L29/04 , H01L27/01 , H01L31/036
CPC分类号： H01L29/78696 , H01L27/1108 , H01L29/41733 , H01L29/66757
摘要： A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).
摘要翻译： 在一个实施例中，通过在覆盖在基板（116）上的电介质层（118）中形成开口（124）来制造具有自对准源区和漏区的薄膜晶体管。 围绕开口（124）的周边（126）并且邻近开口（124）的侧壁（128）形成半导体侧壁间隔物（130）。 第一电极区域（120）在位于开口（124）的仅位于开口的第二侧面半部分（124）的周边（126）的第一位置处电耦合到半导体侧壁间隔件（130）的第一部分 124）。 第二电极区域（122）在位于开口（124）的仅位于开口的第一侧面半部分（124）的周边（126）的第二位置处电连接到半导体侧壁间隔件（130）的第二部分 124）。 邻近半导体侧壁间隔物（130）形成介电层（132）。 与电介质层（132）相邻地形成控制电极（134）。
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公开(公告)号：US5374573A
公开(公告)日：1994-12-20
申请号：US200591
申请日：1994-02-23
IPC分类号： H01L29/78 , H01L21/336 , H01L27/11 , H01L29/417 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L27/1108 , H01L29/41733 , H01L29/66757
摘要： A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).
摘要翻译： 在一个实施例中，通过在覆盖在基板（116）上的电介质层（118）中形成开口（124）来制造具有自对准源区和漏区的薄膜晶体管。 围绕开口（124）的周边（126）并且邻近开口（124）的侧壁（128）形成半导体侧壁间隔物（130）。 第一电极区域（120）在位于开口（124）的仅位于开口的第二侧面半部分（124）的周边（126）的第一位置处电耦合到半导体侧壁间隔件（130）的第一部分 124）。 第二电极区域（122）在位于开口（124）的仅位于开口的第一侧面半部分（124）的周边（126）的第二位置处电连接到半导体侧壁间隔物（130）的第二部分 124）。 邻近半导体侧壁间隔物（130）形成介电层（132）。 与电介质层（132）相邻地形成控制电极（134）。
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10.发明授权Static-random-access memory cell and an integrated circuit having a static-random-access memory cell 失效静态随机存取存储器单元和具有静态随机存取存储单元的集成电路
公开(公告)号：US5485420A
公开(公告)日：1996-01-16
申请号：US278465
申请日：1994-07-21
申请人： Craig S. Lage , Frank K. Baker , James D. Hayden , Kent J. Cooper
发明人： Craig S. Lage , Frank K. Baker , James D. Hayden , Kent J. Cooper
IPC分类号： G11C11/412 , H01L21/8244 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , Y10S257/903
摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.
摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。
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