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137 条记录 (耗时 0.033 秒)

    Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture
    1.
    发明申请
    Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture 失效
    在微处理器流水线架构中避免数据依赖危害的方法和装置

    公开(公告)号：US20060037023A1

    公开(公告)日：2006-02-16

    申请号：US10916188

    申请日：2004-08-11

    申请人： James Dieffenderfer ,  Nathan Nunamaker ,  Sanjay Patel

    发明人： James Dieffenderfer ,  Nathan Nunamaker ,  Sanjay Patel

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3855

    摘要： A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.

    摘要翻译： 一种用于避免通过微处理器管道传播的指令的各种危险的方法和系统。 当流水线内存在多个读取和写入相同值的指令时，建立一个向量来区分较旧的指令。 此外，在分派指令执行之前，生成指针，该指针标识具有所需操作数或参数值的特定指令。 因此，通过监视最近的向量和指针，可以避免日期依赖危害。

    Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor
    2.
    发明申请
    Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor 审中-公开
    在超标量处理器到达调度点之前重新格式化指令的装置和方法

    公开(公告)号：US20060155961A1

    公开(公告)日：2006-07-13

    申请号：US11030339

    申请日：2005-01-06

    申请人： James Dieffenderfer ,  Richard Doing ,  Sanjay Patel ,  Steven Testa ,  Kenichi Tsuchiya

    发明人： James Dieffenderfer ,  Richard Doing ,  Sanjay Patel ,  Steven Testa ,  Kenichi Tsuchiya

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/382

    摘要： Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.

    摘要翻译： 用于在流水线处理器中重新格式化指令的方法和装置。 指令寄存器保存从处理器外部的高速缓冲存储器接收的多个指令。 预解码器对每个指令进行预解码，并从指令操作字段中确定应放置指令字段。 多路复用器将结构化对齐的指令重新格式化为在存储到L1高速缓存之前的硬件实现对准的指令，使得指令准备好发送到流水线执行单元。

    Performance profiling of microprocessor systems using debug hardware and performance monitor
    3.
    发明申请
    Performance profiling of microprocessor systems using debug hardware and performance monitor 审中-公开
    使用调试硬件和性能监视器对微处理器系统进行性能分析

    公开(公告)号：US20060048011A1

    公开(公告)日：2006-03-02

    申请号：US10926566

    申请日：2004-08-26

    申请人： James Dieffenderfer ,  Sanjay Patel ,  Brian Stempel

    发明人： James Dieffenderfer ,  Sanjay Patel ,  Brian Stempel

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3466 ,  G06F11/3648 ,  G06F2201/88

    摘要： A method and system for monitoring the real-time of software running on a microprocessor system. Debug hardware is used to select a range of instructions or events to be monitored by a performance monitor interval with the microprocessor system. A comparison is made between each event and start and stop events are identified in the debug hardware. The performance monitor is enabled by the debug hardware, when events occur within the range defined by the debug hardware. Use of the debug hardware for enabling performance monitoring avoids any overhead associated with generating interrupts, or additional code in the application program.

    摘要翻译： 一种用于监视在微处理器系统上运行的软件的实时的方法和系统。 调试硬件用于通过微处理器系统的性能监视间隔来选择要监视的一系列指令或事件。 在每个事件之间进行比较，并在调试硬件中标识起始和停止事件。 性能监视器由调试硬件启用，当事件发生在调试硬件定义的范围内时。 使用调试硬件实现性能监视可以避免与生成中断或应用程序中的附加代码相关的任何开销。

    Apparatus and method for guest and root register sharing in a virtual machine
    6.
    发明授权
    Apparatus and method for guest and root register sharing in a virtual machine 有权
    在虚拟机中访客和根寄存器共享的装置和方法

    公开(公告)号：US09086906B2

    公开(公告)日：2015-07-21

    申请号：US13436654

    申请日：2012-03-30

    申请人： Sanjay Patel ,  Ranjit Joseph Rozario

    发明人： Sanjay Patel ,  Ranjit Joseph Rozario

    IPC分类号： G06F9/455

    CPC分类号： G06F9/4555

    摘要： A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

    摘要翻译： 计算机可读存储介质包括可执行指令，以定义具有访客模式控制寄存器的处理器，所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定 访客模式控制寄存器包括一个控制位，用于指定访客阻止寄存器状态和共享寄存器状态。 根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。 根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。 访客环境和根本环境支持硬件资源的虚拟化，使得支持多个应用的​​多个操作系统由硬件资源执行。

    Nanonized Iron Compositions and Methods of Use Thereof
    8.
    发明申请
    Nanonized Iron Compositions and Methods of Use Thereof 审中-公开
    纳米铁组合物及其使用方法

    公开(公告)号：US20120177700A1

    公开(公告)日：2012-07-12

    申请号：US13338210

    申请日：2011-12-27

    申请人： Mir A. Imran ,  Mir Hashim ,  Lu Wang ,  Sanjay Patel ,  Joel M. Harris ,  Phil Morgan

    发明人： Mir A. Imran ,  Mir Hashim ,  Lu Wang ,  Sanjay Patel ,  Joel M. Harris ,  Phil Morgan

    IPC分类号： A61K9/00 ,  A61K33/42 ,  B82Y5/00

    CPC分类号： A61K9/14 ,  A61K33/26

    摘要： Embodiments of the invention provide nanonized iron compositions for treatment of iron deficiency such as iron deficiency anemia. Many embodiments provide nanonized iron compositions which are sized to minimize adverse reaction such as immune response, adverse GI reaction and allergic reaction to iron compound included in the composition. The nanonized iron compositions can be used in a variety of drug delivery forms, including an oral dosage form, a transdermal patch, in an intravenous solution or in a dialysate for treatment of a patient with chronic kidney disease (CKD). Embodiments of the invention also provide methods of using the nanonized iron compositions for the treatment of iron deficiency in a patient in need thereof including patients with iron deficiency anemia and CKD.

    摘要翻译： 本发明的实施方案提供了用于治疗铁缺乏症（例如缺铁性贫血）的纳米铁组合物。 许多实施方案提供纳米级铁组合物，其尺寸设定成使包括在组合物中的铁化合物的不良反应如免疫应答，不良GI反应和过敏反应最小化。 纳米铁组合物可以以各种药物递送形式使用，包括口服剂型，透皮贴剂，静脉内溶液或用于治疗慢性肾脏病（CKD）患者的透析液。 本发明的实施方案还提供了使用纳米铁组合物治疗需要其的患者缺铁的方法，包括缺铁性贫血和CKD患者。

    Resource sharing to reduce implementation costs in a multicore processor
    9.
    发明授权
    Resource sharing to reduce implementation costs in a multicore processor 有权
    资源共享以降低多核处理器中的实施成本

    公开(公告)号：US08195883B2

    公开(公告)日：2012-06-05

    申请号：US12694877

    申请日：2010-01-27

    申请人： Prashant Jain ,  Yoganand Chillarige ,  Sandip Das ,  Shukur Moulali Pathan ,  Srinivasan R. Iyengar ,  Sanjay Patel

    发明人： Prashant Jain ,  Yoganand Chillarige ,  Sandip Das ,  Shukur Moulali Pathan ,  Srinivasan R. Iyengar ,  Sanjay Patel

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0811 ,  G06F12/0813

    摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

    摘要翻译： 处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。 控制器可以共享对耦合到互连网络的互连出口端口的访问，并且可以生成多个并发请求以经由共享端口传送数据，其中每个请求去往相应的核心，并且其中端口的数据路径宽度 小于多个请求的组合宽度。 给定标签单元可以在控制器之间仲裁以访问共享端口，使得请求被串行地发送到相应的核心而不是同时发送。