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    In-system reconfigurable circuit for mapping data words of different lengths
    1.
    发明授权
    In-system reconfigurable circuit for mapping data words of different lengths 有权
    用于映射不同长度的数据字的系统内可重构电路

    公开(公告)号：US08823561B1

    公开(公告)日：2014-09-02

    申请号：US13452060

    申请日：2012-04-20

    申请人： Michael Hammer ,  David Pierce ,  Jin Zhang

    发明人： Michael Hammer ,  David Pierce ,  Jin Zhang

    IPC分类号： H03M7/40

    CPC分类号： H04J3/1605 ,  H04J3/047 ,  H04W28/065 ,  H04W88/085

    摘要： A de-mapping circuit for de-mapping input words of a first length into output words of a second length different from the first length. In one embodiment, the circuit includes a word register of the first length and temporary registers of the second length. The word register successively stores each of the inputs words in response to cycles of a clock. The temporary registers temporarily store the output words. Multiplexers configured by address signals select bits from stored input words and store the selected bits into the temporary registers to form temporarily stored output words.

    摘要翻译： 一种用于将第一长度的输入字解映射成与第一长度不同的第二长度的输出字的去映射电路。 在一个实施例中，电路包括第一长度的字寄存器和第二长度的临时寄存器。 字寄存器响应于时钟的周期而连续地存储每个输入字。 临时寄存器临时存储输出字。 由地址信号配置的多路复用器从存储的输入字中选择位，并将所选位存储到临时寄存器中以形成临时存储的输出字。

    In-system reconfigurable circuit for mapping data words of different lengths
    2.
    发明授权
    In-system reconfigurable circuit for mapping data words of different lengths 有权
    用于映射不同长度的数据字的系统内可重构电路

    公开(公告)号：US08165164B1

    公开(公告)日：2012-04-24

    申请号：US12494822

    申请日：2009-06-30

    申请人： Michael Hammer ,  David Pierce ,  Jin Zhang

    发明人： Michael Hammer ,  David Pierce ,  Jin Zhang

    IPC分类号： H04J3/24

    CPC分类号： H04J3/1605 ,  H04J3/047 ,  H04W28/065 ,  H04W88/085

    摘要： A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first data words. The mapping and de-mapping is responsive to address signals that may be stored in a memory such that a desired mapping or de-mapping corresponds to a particular programming of the memory. In this fashion, the mapping and de-mapping is in-system reconfigurable.

    摘要翻译： 提供映射电路用于将第一数据字映射到第二数据字的帧，其中第一和第二数据字的长度不同。 另外，提供去映射电路用于将第二数据字的帧解映射成第一数据字。 映射和解映射响应于可存储在存储器中的地址信号，使得期望的映射或解映射对应于存储器的特定编程。 以这种方式，映射和映射是系统内可重新配置的。

    Logic analyzer systems and methods for programmable logic devices
    3.
    发明授权
    Logic analyzer systems and methods for programmable logic devices 有权
    用于可编程逻辑器件的逻辑分析仪系统和方法

    公开(公告)号：US07536615B1

    公开(公告)日：2009-05-19

    申请号：US11691003

    申请日：2007-03-26

    申请人： David Pierce ,  Michael Hammer ,  Brian M. Caslis

    发明人： David Pierce ,  Michael Hammer ,  Brian M. Caslis

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177

    摘要： A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.

    摘要翻译： 根据一个实施例，可编程逻辑器件包括多个逻辑块; 适于在逻辑块之间路由信号的互连结构; 以及用于在可编程逻辑器件内存储数据的存储器。 第一组逻辑块被配置为逻辑分析器触发单元，其适于每个从可编程逻辑器件中接收一个或多个输入信号，并提供相应的触发单元输出信号。 存储器的一部分存储逻辑分析器触发表达式，触发单元输出信号作为触发表达式的地址信号提供给存储器。

    Logic analyzer systems and methods for programmable logic devices
    4.
    发明授权
    Logic analyzer systems and methods for programmable logic devices 有权
    用于可编程逻辑器件的逻辑分析仪系统和方法

    公开(公告)号：US07743296B1

    公开(公告)日：2010-06-22

    申请号：US11691040

    申请日：2007-03-26

    申请人： David Pierce ,  Michael Hammer ,  Brian M. Caslis

    发明人： David Pierce ,  Michael Hammer ,  Brian M. Caslis

    IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F9/455 ,  G06F7/38 ,  G06F17/50 ,  G06F9/45 ,  H03K17/693 ,  H03K19/177 ,  H03K19/173 ,  H03K19/00

    CPC分类号： G06F17/5027 ,  H03K19/177

    摘要： A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.

    摘要翻译： 根据实施例的编程可编程逻辑器件（PLD）的方法包括经由用于监视内部PLD信号的软件接口接收逻辑分析器的触发单元信息，并且基于用于所述内部PLD信号的内部PLD信号提供触发单元输出信号 相应的触发单位; 并通过软件接口作为逻辑运算符和操作数的文本串接收逻辑分析仪的触发表达式信息，其中操作数表示触发单元输出信号。 该方法还可以包括：基于触发单元信息和触发表情信息生成配置数据; 以及向PLD提供配置数据，其中基于触发表达信息的触发表达式被存储在PLD的存储器内。

    Correlator having user-defined processing
    5.
    发明授权
    Correlator having user-defined processing 有权
    相关器具有用户定义的处理

    公开(公告)号：US07606851B2

    公开(公告)日：2009-10-20

    申请号：US11202149

    申请日：2005-08-10

    申请人： David Pierce ,  Michael Hammer

    发明人： David Pierce ,  Michael Hammer

    IPC分类号： G06F17/15

    CPC分类号： G06F17/15

    摘要： In one embodiment of the invention, a circuit may include and/or involve a correlator, a programmable fabric, and logic to enable selection of one of default processing logic and alternate processing logic to process corresponding data and coefficient values of the correlator.

    摘要翻译： 在本发明的一个实施例中，电路可以包括和/或涉及相关器，可编程结构和逻辑，以使得能够选择默认处理逻辑和备用处理逻辑之一来处理相关器的对应数据和系数值。

    Correlator having user-defined processing
    6.
    发明申请
    Correlator having user-defined processing 有权
    相关器具有用户定义的处理

    公开(公告)号：US20070038692A1

    公开(公告)日：2007-02-15

    申请号：US11202149

    申请日：2005-08-10

    申请人： David Pierce ,  Michael Hammer

    发明人： David Pierce ,  Michael Hammer

    IPC分类号： G06F17/15

    CPC分类号： G06F17/15

    摘要： In one embodiment of the invention, a circuit may include and/or involve a correlator, a programmable fabric, and logic to enable selection of one of default processing logic and alternate processing logic to process corresponding data and coefficient values of the correlator.

    摘要翻译： 在本发明的一个实施例中，电路可以包括和/或涉及相关器，可编程结构和逻辑，以使得能够选择默认处理逻辑和备用处理逻辑之一来处理相关器的对应数据和系数值。

    PROCESSES FOR MOLDING PULP PAPER CONTAINERS AND LIDS
    8.
    发明申请
    PROCESSES FOR MOLDING PULP PAPER CONTAINERS AND LIDS 审中-公开
    用于模制纸浆容器和小袋子的方法

    公开(公告)号：US20110011549A1

    公开(公告)日：2011-01-20

    申请号：US12821054

    申请日：2010-06-22

    申请人： David Pierce ,  Edward Urquhart

    发明人： David Pierce ,  Edward Urquhart

    IPC分类号： D21J3/00

    CPC分类号： D21J3/10

    摘要： A process for molding recyclable, compostable, and disposable containers made of pulp paper is disclosed herein. The process includes disposing a wet pulp layer on a male or female mold, mating the mold with its counterpart, and applying a force on the pulp layer to remove moisture and thin the pulp. The process continues by applying a vacuum to either the male or female mold to hold the pulp layer, and removing the other mold. The process further comprises sequentially mating male and female molds until the pulp layer is the desired thickness and shape of the container. Embodiments of the process may include molding pulp containers to include pleats, stability features, reverse draft features, and puffed pulp configurations.

    摘要翻译： 本文公开了由纸浆纸制成的可回收，可堆肥和一次性容器的成型方法。 该方法包括将湿纸浆层设置在阳模或阴模上，使模具与其对应物配合，并在纸浆层上施加力以除去水分并使纸浆变薄。 该方法通过对阳模或阴模施加真空以保持纸浆层，并且移除另一个模具继续进行。 该方法还包括顺序地配合阳模和阴模，直到纸浆层为容器的所需厚度和形状。 该方法的实施方案可以包括成型纸浆容器以包括褶皱，稳定性特征，反向牵伸特征和膨化纸浆构造。

    Automated accellerated extraction of trace elements from biomass
    9.
    发明申请
    Automated accellerated extraction of trace elements from biomass 有权
    从生物质中自动提取微量元素

    公开(公告)号：US20060283813A1

    公开(公告)日：2006-12-21

    申请号：US11471224

    申请日：2006-06-20

    申请人： David Pierce ,  Wayne Seames

    发明人： David Pierce ,  Wayne Seames

    IPC分类号： F01N3/20

    CPC分类号： G01N31/005

    摘要： A method and apparatus automates and accelerates the extraction and analysis of trace elements from biomass. The method and apparatus are especially useful at key segregation points in the food chain where speed and accuracy is necessary to separate agricultural cereals that are elevated in beneficial trace element content which provides higher value to the producer.

    摘要翻译： 一种方法和设备可以自动化并加速从生物质中提取和分析微量元素。 该方法和装置在食物链中的关键分离点特别有用，其中需要速度和准确性来分离提供较高价值的有益微量元素含量的农业谷物。