公开(公告)号：US20060249813A1

公开(公告)日：2006-11-09

申请号：US10908361

申请日：2005-05-09

申请人： James Dunn ,  David Harame ,  Jeffrey Johnson ,  Alvin Joseph

发明人： James Dunn ,  David Harame ,  Jeffrey Johnson ,  Alvin Joseph

IPC分类号： H01L27/082

CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

公开(公告)号：US20060081934A1

公开(公告)日：2006-04-20

申请号：US11289915

申请日：2005-11-30

申请人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen Onge ,  Andreas Stricker

发明人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen Onge ,  Andreas Stricker

IPC分类号： H01L23/62

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

公开(公告)号：US20050048735A1

公开(公告)日：2005-03-03

申请号：US10604988

申请日：2003-08-29

申请人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen St. Onge ,  Andreas Stricker

发明人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen St. Onge ,  Andreas Stricker

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L21/76

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

公开(公告)号：US20070264787A1

公开(公告)日：2007-11-15

申请号：US11830376

申请日：2007-07-30

申请人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

发明人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

公开(公告)号：US20060060886A1

公开(公告)日：2006-03-23

申请号：US10711486

申请日：2004-09-21

申请人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

发明人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

公开(公告)号：US20070190692A1

公开(公告)日：2007-08-16

申请号：US11275542

申请日：2006-01-13

申请人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

发明人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

IPC分类号： H01L21/50

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

公开(公告)号：US20060177986A1

公开(公告)日：2006-08-10

申请号：US11378927

申请日：2006-03-17

申请人： Alvin Joseph ,  Qizhi Liu

发明人： Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L21/8222

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/732

摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

摘要翻译： 高电平和高压双极晶体管包括发射极，基极和集电极。 发射器具有延伸超出下部的下部和上部。 基础包括内在基础和外在碱基。 本征基极位于发射极的下部和集电极之间。 外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。 连续导体提供从底部触点（未示出）到本征基极的低电阻路径。 晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。

公开(公告)号：US20060060887A1

公开(公告)日：2006-03-23

申请号：US10711482

申请日：2004-09-21

申请人： Peter Geiss ,  Alvin Joseph ,  Rajendran Krishnasamy ,  Xuefeng Liu

发明人： Peter Geiss ,  Alvin Joseph ,  Rajendran Krishnasamy ,  Xuefeng Liu

IPC分类号： H01L31/109

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

摘要翻译： 在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。 在基板上形成基极区域，在基极区域上形成发射极区域。 集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。 提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。

公开(公告)号：US20060249850A1

公开(公告)日：2006-11-09

申请号：US10908354

申请日：2005-05-09

申请人： Mete Erturk ,  Alvin Joseph ,  Anthony Stamper

发明人： Mete Erturk ,  Alvin Joseph ,  Anthony Stamper

IPC分类号： H01L23/52

CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.

摘要翻译： 公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。 接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。 接地屏蔽在第一金属（M 1）级别提供低电阻，非常厚的金属，用于与标准后端（BEOL）集成结合的无源RF元件。 本发明还包括形成接地屏蔽的方法。

公开(公告)号：US20060124964A1

公开(公告)日：2006-06-15

申请号：US11288843

申请日：2005-11-29

申请人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

发明人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L31/109

CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.