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公开(公告)号：US07684533B2
公开(公告)日：2010-03-23
申请号：US11457161
申请日：2006-07-13
IPC分类号： H04L7/00
CPC分类号： H03L7/08
摘要： A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal. An analysis logic circuit is provided having a plurality of n inputs connected to the outputs of the latches. The analysis logic circuit analyzes the values on the latches to give a measure of jitter.
摘要翻译： 一种抖动测量电路和方法，具有用于接收其测试抖动的参考信号的输入端，用于接收具有一系列周期的时钟信号的输入端和用于测量参考信号和时钟信号之间的延迟的测量电路 在循环周期基础上，给出周期抖动测量的周期。 测量电路包括多个n级，每级具有包括输入的延迟元件。 第二和稍后的延迟元件的输入连接到前一级的输出，第一延迟元件具有用于接收参考信号的输入。 n个锁存器中的一个连接到对应的一个延迟元件的输入端。 每个锁存器具有用于接收时钟信号的时钟输入端，以及当时钟输入由时钟信号的边沿计时时，用于锁存锁存器输入端的值的输出端。 提供分析逻辑电路，其具有连接到锁存器的输出的多个n个输入。 分析逻辑电路分析锁存器上的值以给出抖动的度量。
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公开(公告)号：US08237513B2
公开(公告)日：2012-08-07
申请号：US12821526
申请日：2010-06-23
CPC分类号： H03L3/00
摘要： A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.
摘要翻译： 用于锁相环（PLL）的压控振荡器（VCO）包括启动振荡器，所述启动振荡器包括第一多个反相器; 主振荡器，所述主振荡器包括第二多个反相器，其中所述第二多个反相器的数量少于所述第一多个反相器的数量; 以及连接到启动振荡器和主振荡器的控制模块。 一种在锁相环（PLL）中操作压控振荡器（VCO）的方法，包括启动振荡器和主振荡器的VCO包括向启动振荡器发送使能信号; 等待预定数量的启动振荡器时钟周期; 并且当经过预定数量的启动振荡器时钟周期时，向启动振荡器发送禁止信号，并向主振荡器发送使能信号。
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公开(公告)号：US20090189591A1
公开(公告)日：2009-07-30
申请号：US12021484
申请日：2008-01-29
CPC分类号： G05F3/30
摘要： In temperature sensing circuitry PTAT (Proportional to Absolute Temperature) Voltage References are typically used. By adding a feedback circuit and a source follower into the classic design, the circuit can guarantee that the current is mirrored identically regardless of the value of power supply voltage. This added circuitry is easy to implement and is low in both power and area. The essence of this invention is that the PTAT circuit allows a large range of operation including low voltage (1 Volt) and more accurate temperature readings.
摘要翻译： 在温度感测电路PTAT（与绝对温度成比例）中，通常使用电压基准。 通过在经典设计中添加反馈电路和源极跟随器，电路可以保证电流相同，无论电源电压的值如何。 这种增加的电路容易实现，功率和面积都很小。 本发明的实质是PTAT电路允许包括低电压（1伏）和更准确的温度读数的大范围的操作。
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公开(公告)号：US07777475B2
公开(公告)日：2010-08-17
申请号：US12021484
申请日：2008-01-29
CPC分类号： G05F3/30
摘要： A method and apparatus for generating a voltage that is proportional to an absolute temperature (PTAT voltage). A current generator for generating a current that is proportional to absolute temperature (PTAT current) has an internal resistance and two diodes. The PTAT current is proportional to the resistance, and the temperature coefficient of the PTAT current is defined by the ratio of diode current densities. A feedback circuit has a source follower that is connected to the current generator for driving the output node with a regulated PTAT current wherein the PTAT current is mirrored accurately, providing a constant Vref.
摘要翻译： 一种用于产生与绝对温度（PTAT电压）成比例的电压的方法和装置。 用于产生与绝对温度（PTAT电流）成比例的电流的电流发生器具有内部电阻和两个二极管。 PTAT电流与电阻成正比，PTAT电流的温度系数由二极管电流密度的比值定义。 反馈电路具有连接到电流发生器的源极跟随器，用于利用调节的PTAT电流驱动输出节点，其中PTAT电流被精确地镜像，提供恒定的Vref。
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5.发明授权Circuits associated with fusible elements for establishing and detecting of the states of those elements 失效与可熔元件相关联的电路，用于建立和检测这些元件的状态公开(公告)号：US07084696B2
公开(公告)日：2006-08-01
申请号：US10819865
申请日：2004-04-07
IPC分类号： H01H37/76
CPC分类号： H01L23/544 , G06K19/067 , G11C17/18 , H01L23/5256 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A state detection circuit for a fusible element includes a differential sensing circuit that compares voltage at a detection point in a path containing the fusible element with that at a reference point in a path establishing a non-zero reference voltage. The paths are similarly configured except one contains the fusible element while the other contains a device establishing the reference voltage. The two paths in any given sensing circuit are located in close proximity to each other so that even though element parameters in the paths of different sensing circuits may vary significantly, those values track each other in the given sensing circuit. As a result, the normal non-zero value of the voltage at the reference point maintains a relationship to that at the detection point that enables the differential sensing circuit to detect between a fused and an unfused element irrespective of variation in circuit element parameters. In order to prevent detection circuits and other circuits on the chip being damaged, during blowing of the fusible elements, voltage level of the sensing circuits are chosen to isolate the detection circuits from the other circuits on the semiconductor chip and the excitation levels applied to the detection circuits are raised to maintain differential voltages in the detection circuits at sufficiently low levels to prevent damage.
摘要翻译： 用于可熔元件的状态检测电路包括差分感测电路，其将包含可熔元件的路径中的检测点处的电压与建立非零参考电压的路径中的参考点处的电压进行比较。 除了一个包含可熔元件，而另一个包含建立参考电压的器件之外，这些路径被类似地配置。 任何给定的感测电路中的两条路径彼此靠近，使得尽管不同感测电路的路径中的元件参数可能会显着变化，但是这些值在给定的感测电路中彼此跟踪。 结果，参考点处的电压的正常非零值保持与检测点的正常非零值，使得差分感测电路能够检测融合元件和未熔接元件之间，而与电路元件参数的变化无关。 为了防止芯片上的检测电路和其他电路被损坏，在吹制可熔元件期间，选择感测电路的电压电平以将检测电路与半导体芯片上的其他电路隔离，并且施加到 提高检测电路以将检测电路中的差分电压保持在足够低的水平以防止损坏。
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公开(公告)号：US20110316593A1
公开(公告)日：2011-12-29
申请号：US12821526
申请日：2010-06-23
IPC分类号： H03L7/06
CPC分类号： H03L3/00
摘要： A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.
摘要翻译： 用于锁相环（PLL）的压控振荡器（VCO）包括启动振荡器，所述启动振荡器包括第一多个反相器; 主振荡器，所述主振荡器包括第二多个反相器，其中所述第二多个反相器的数量少于所述第一多个反相器的数量; 以及连接到启动振荡器和主振荡器的控制模块。 一种在锁相环（PLL）中操作压控振荡器（VCO）的方法，包括启动振荡器和主振荡器的VCO包括向启动振荡器发送使能信号; 等待预定数量的启动振荡器时钟周期; 并且当经过预定数量的启动振荡器时钟周期时，向启动振荡器发送禁止信号，并向主振荡器发送使能信号。
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7.发明授权PLL loop filter capacitor test circuit and method for on chip testing of analog leakage of a circuit 失效PLL环路滤波电容测试电路及芯片模拟电路漏电测试方法公开(公告)号：US07078887B1
公开(公告)日：2006-07-18
申请号：US11040138
申请日：2005-01-21
IPC分类号： G01R23/12
CPC分类号： G01R27/02 , G01R31/2639 , G01R31/2884
摘要： A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers. The reference resistor circuit is broken into several series resistors and additional transistors and resistors are supplied with their terminals shorted out, to allow for RIT-B circuit tuning. The output of the test circuit provides the measurement of analog leakage to a digital tester for testing of chips having the circuit during manufacturing test.
摘要翻译： 现有设计中的测试电路，使测试电路能够在电路内直接测试。 本发明提供了一种在使用现有引脚的简单数字测试仪中测试和测量测试期间PLL环路滤波电容器漏电泄漏的方法。 测试PLL电路具有用于测量泄漏的多个电容器和响应放大器电路，包括具有串联耦合的多个晶体管的第一电容器组和耦合到第一放大器的参考电阻器电路和具有串联耦合的多个晶体管的第二电容器组 并且所述参考电阻器电路耦合到第二放大器以测量穿过耦合到所述第一和第二放大器的相应电容器的泄漏，并且提供所述泄漏的输出与所述第一和第二放大器的输出进行测量。 参考电阻电路分为几个串联电阻，额定的晶体管和电阻的端子短路，以允许RIT-B电路调谐。 测试电路的输出提供了对数字测试仪的模拟泄漏测量，用于在制造测试期间测试具有电路的芯片。
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公开(公告)号：US6141632A
公开(公告)日：2000-10-31
申请号：US388594
申请日：1999-09-02
申请人： George E. Smith, III , Fariborz Assaderaghi , Paul D. Muench , Lawrence F. Wagner, Jr. , Timothy L. Walters
发明人： George E. Smith, III , Fariborz Assaderaghi , Paul D. Muench , Lawrence F. Wagner, Jr. , Timothy L. Walters
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, delay rules generation), the offset from the body voltage as a part of the best case/worst case determination is included. The improved process employs a topological analysis for circuit elements to determine whether the element falls in one of several categories, and in the process determines which elements of a circuit might be in AC equilibrium.
摘要翻译： 用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括通过在仿真期间的任何时间对浮动体电压进行模拟并将浮体电压设置为任何期望值，通过向模型添加 理想的电压源，其值是期望的体电压，与理想电流源串联，其值是恒定倍数自身的电压。 当常数为零时，不会流过电流，任何附加组件对电路都没有影响。 当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出身体节点，从而设定其电压。 恒定值始终保持为零，除非需要改变体电压。 可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。 为了解决预测延迟预测器中的延迟（例如，延迟规则生成）的问题，包括作为最佳情况/最坏情况确定的一部分的与体电压的偏移。 改进的过程采用电路元件的拓扑分析来确定元件是否属于几个类别之一，并且在该过程中确定电路的哪些元件可能处于AC平衡状态。
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公开(公告)号：US07271643B2
公开(公告)日：2007-09-18
申请号：US11138102
申请日：2005-05-26
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically blowable fuse circuit having a fuse which may be placed in a condition to be blown. The circuit includes a first transistor having a body, a source, a drain, and a gate. The source is connected to one end of the fuse and the drain is connected to ground. The first transistor further includes a controllable parasitic device in its body. A second transistor is connected to the parasitic device such that when the second transistor is turned on, the parasitic device turns on the first transistor, allowing the fuse to be blown when the fuse is placed in a condition to be blown.
摘要翻译： 一种具有熔断器的可电熔熔断器电路，该保险丝可被放置在要被吹制的状态。 电路包括具有主体，源极，漏极和栅极的第一晶体管。 源极连接到保险丝的一端，漏极连接到地。 第一晶体管还包括其体内的可控寄生器件。 第二晶体管连接到寄生器件，使得当第二晶体管导通时，寄生器件接通第一晶体管，当保险丝置于待熔断状态时，允许保险丝熔断。
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公开(公告)号：US6023577A
公开(公告)日：2000-02-08
申请号：US938676
申请日：1997-09-26
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, NDR rules generation), the offset from the body voltage as a part of the best case/worst case determination is included.
摘要翻译： 用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括在模拟期间的任何时间，模拟SOI器件并将浮动体电压设置为任何所需值，通过向模型添加理想 电压源，其值是期望的体电压，与理想电流源串联，其值为恒定倍数的电压。 当常数为零时，电流不能流动，任何附加的组件对电路都没有影响。 当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出体节点，从而设定其电压。 恒定值始终保持为零，除非需要改变体电压。 可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。 为了解决预测延迟预测器中的延迟（例如，NDR规则生成）的问题，包括作为最佳情况/最坏情况判定的一部分的与体电压的偏移。
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