Method for enhancing electrode surface area in DRAM cell capacitors

    公开(公告)号:US07148555B2

    公开(公告)日:2006-12-12

    申请号:US10408358

    申请日:2003-04-07

    IPC分类号: H01L29/00

    摘要: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

    Method for enhancing electrode surface area in DRAM cell capacitors
    3.
    发明授权
    Method for enhancing electrode surface area in DRAM cell capacitors 失效
    提高DRAM单元电容器电极表面积的方法

    公开(公告)号:US07573121B2

    公开(公告)日:2009-08-11

    申请号:US11514694

    申请日:2006-08-31

    IPC分类号: H01L29/94

    摘要: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

    摘要翻译: 提供了形成半导体电路中的电容器的下电极的方法以及通过这些方法形成的电容器。 下电极通过形成纹理化的底层然后在其上沉积导电材料来制造。 在形成下电极的方法的一个实施方案中,通过在容器的绝缘层上沉积包含烃嵌段和含硅嵌段的聚合材料,然后随后将聚合物膜转化为浮雕而形成该组织化层 或通过暴露于UV辐射和臭氧的多孔纳米结构,导致织构化的多孔或缓蚀硅碳化硅膜。 然后将导电材料沉积在纹理化层上,导致下部电极具有上部粗糙表面。 在形成下电极的方法的另一实施例中,通过沉积覆盖的第一和第二导电金属层并退火金属层形成优选构造为周期性网络的表面位错来形成纹理化下层。 然后将导电金属沉积在气相中,并且聚集到构造层的表面位错上,形成岛簇形式的纳米结构。 电容器通过在形成的下电极上沉积介电层并在电介质层上形成上电容器电极来完成。 电容器在制造DRAM单元时特别有用。