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    Localized masking for semiconductor structure development
    1.
    发明授权
    Localized masking for semiconductor structure development 失效
    半导体结构开发的局部掩蔽

    公开(公告)号：US07468534B2

    公开(公告)日：2008-12-23

    申请号：US11216417

    申请日：2005-08-30

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L27/108

    CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

    Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

    Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

    MRAM device for preventing electrical shorts during fabrication
    2.
    发明授权
    MRAM device for preventing electrical shorts during fabrication 有权
    用于在制造期间防止电气短路的MRAM装置

    公开(公告)号：US07285811B2

    公开(公告)日：2007-10-23

    申请号：US11513244

    申请日：2006-08-31

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L29/76 ,  H01L21/00

    CPC classification number: H01L27/222 ,  H01L43/12

    Abstract: The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. A first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is patterned and etched to form an opening over the first conductor for the cell shapes. The magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

    Abstract translation: 本发明提供一种在制造期间使电短路发生最小化的MRAM电池。 第一导体设置在绝缘层中的沟槽中，并且绝缘层的上表面和第一导体被平坦化。 第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元的厚度的厚度。 图案化和蚀刻第一介电层以在单元形状的第一导体上形成开口。 包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

    Methods of fabricating an MRAM device using chemical mechanical polishing
    4.
    发明授权
    Methods of fabricating an MRAM device using chemical mechanical polishing 有权
    使用化学机械抛光制造MRAM器件的方法

    公开(公告)号：US06673675B2

    公开(公告)日：2004-01-06

    申请号：US10119952

    申请日：2002-04-11

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L21336

    CPC classification number: H01L27/222 ,  H01L43/12

    Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

    Abstract translation: 本发明提供一种形成MRAM单元的方法，该方法在制造期间使电短路的发生最小化。 第一导体设置在绝缘层中的沟槽中，并且绝缘层的上表面和第一导体被平坦化。 然后，将第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元厚度的厚度。 然后对第一介电层进行图案化和蚀刻，以在单元形状的第一导体上形成开口。 然后，包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

    LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT
    6.
    发明申请
    LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT 有权
    用于半导体结构开发的本地化掩模

    公开(公告)号：US20090102018A1

    公开(公告)日：2009-04-23

    申请号：US12276152

    申请日：2008-11-21

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L29/92

    CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

    Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

    Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

    Enhanced surface area capacitor fabrication methods
    7.
    发明授权
    Enhanced surface area capacitor fabrication methods 失效
    增强表面积电容器制造方法

    公开(公告)号：US07112503B1

    公开(公告)日：2006-09-26

    申请号：US09653156

    申请日：2000-08-31

    Applicant: Vishnu K. Agarwal ,  Garry A. Mercaldi

    Inventor： Vishnu K. Agarwal ,  Garry A. Mercaldi

    IPC: H01L21/20

    CPC classification number: H01L28/55 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

    Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

    Abstract translation: 电容器制造方法可以包括在第一电极上的氧扩散的原子层沉积导电阻挡层。 一种方法可以包括在第一电极上化学吸附至少一层单层的第一前体层，并化学吸附第一前体层上至少一层单层的第二前体层，第一和第二前体层的化学吸附产物 由导电阻挡材料层组成。 阻挡层可以是足够厚且致密的，以通过从阻挡层上方的氧扩散来减少第一电极的氧化。 替代方法可以包括在衬底上形成第一电容器电极，第一电极具有每单位面积的内表面积和每单位面积的外表面积，其大于衬底每单位面积的外表面积。 可以在电介质层上形成电容器电介质层和第二电容器电极。 该方法还可以包括在衬底上形成坚固的多晶硅，第一电极在坚固的多晶硅之上。 因此，第一电极的外表面积可以比不含第一电极包括多晶硅的衬底的外表面积大至少30％。

    Low selectivity deposition methods
    9.
    发明授权
    Low selectivity deposition methods 失效

    公开(公告)号：US06987073B2

    公开(公告)日：2006-01-17

    申请号：US10299140

    申请日：2002-11-18

    Applicant: Garry A. Mercaldi

    Inventor： Garry A. Mercaldi

    IPC: H01L21/31

    CPC classification number: H01L21/02271 ,  C23C16/0272 ,  C23C16/45525 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/3185 ,  H01L28/84 ,  H01L28/91

    Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer. The first and second part of the nucleation layer may be formed simultaneously.

    Semiconductor processing methods and semiconductor defect detection methods
    10.
    发明授权
    Semiconductor processing methods and semiconductor defect detection methods 失效
    半导体处理方法和半导体缺陷检测方法

    公开(公告)号：US06417015B2

    公开(公告)日：2002-07-09

    申请号：US09870157

    申请日：2001-05-29

    Applicant: Michael Nuttall ,  Garry A. Mercaldi

    Inventor： Michael Nuttall ,  Garry A. Mercaldi

    IPC: H01L2166

    CPC classification number: H01L22/24 ,  Y10S438/928 ,  Y10S438/974

    Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon containing material.

    Abstract translation: 描述半导体处理方法和缺陷检测方法。 在一个实施例中，提供了工艺中的半导体晶片，并且在晶片上形成或沉积材料。 该材料可辨别地沉积在缺陷晶片表面区域上，并且不会明显地沉积在无缺陷晶片表面区域上。 随后，检查晶片表面区域以识别缺陷区域。 在另一个实施例中，提供具有包含表面缺陷的暴露区域的衬底。 缺陷突出材料基本上选择性地沉积在表面缺陷上，而不是明显地超过其它暴露区域。 随后检查衬底以便沉积的缺陷突出材料。 在另一个实施例中，在衬底外表面上形成电介质层，并且以可以产生多个随机分布的电介质层特征的方式处理衬底。 基本上选择性地沉积含硅材料并将其接收在随机分布的介电层特征上而不是在其它衬底区域上。 随后检查衬底以选择沉积含硅材料。

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