-
1.发明授权Adapter for interleaving second data with first data already transferred between first device and second device without having to arbitrate for ownership of communications channel 失效用于将第二数据与在第一设备和第二设备之间已经传送的第一数据进行交织的适配器，而不必仲裁通信信道的所有权
公开(公告)号：US5535333A
公开(公告)日：1996-07-09
申请号：US40317
申请日：1993-03-30
申请人： James J. Allen, Jr. , Ronald J. Cooper , Douglas H. Cox , William L. McNeil , Herbert Rivera-Sanchez , Terri L. Tomlinson
发明人： James J. Allen, Jr. , Ronald J. Cooper , Douglas H. Cox , William L. McNeil , Herbert Rivera-Sanchez , Terri L. Tomlinson
CPC分类号： G06F13/32 , G06F13/282
摘要： A system and method for controlling a communications adapter interface such that supplemental data can be interleaved with data being transferred. The interleaving is performed in a manner such that the supplemental data is transparent to the data mover portion of the communications adapter. The supplemental data can be transferred in either read or write cycles that are interleaved at the beginning, in the middle, or at the end of data bursts or block data transfers. As a result of the interleaving, the slave interface bus is more fully utilized because arbitration and bus ownership changes do not create unused cycles. The interleaving is accomplished by temporarily halting an existing transfer of data and transferring the requested supplemental data while the data transfer is halted. After the supplemental data is transferred, the transfer of the balance of the data block is then allowed to continue. In other words, the present invention "steals" a cycle from the data transferror and uses this cycle to transfer supplemental data.
摘要翻译： 一种用于控制通信适配器接口的系统和方法，使得补充数据可以与正在传送的数据交错。 以使得补充数据对于通信适配器的数据移动器部分是透明的方式执行交织。 补充数据可以以在数据突发或块数据传输的开始，中间或结束处交织的读取或写入周期中传送。 作为交错的结果，从接口总线被更充分地利用，因为仲裁和总线所有权的改变不会产生未使用的周期。 通过在数据传送停止的同时临时停止数据的传送和传送所请求的补充数据来完成交织。 在补充数据被传送之后，数据块的余额的传送被允许继续。 换句话说，本发明“从窃取”数据传输的循环，并且使用该周期来传送补充数据。
-
公开(公告)号：US08032713B2
公开(公告)日：2011-10-04
申请号：US12115146
申请日：2008-05-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路 根据投机访问阈值访问和推测访问。
-
3.发明授权Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 有权在可变延迟模式下工作的FBDIMM存储器系统中数据总线带宽调度的结构公开(公告)号：US08028257B2
公开(公告)日：2011-09-27
申请号：US12110765
申请日：2008-04-28
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译： 提供了一种体现在机器可读存储介质中的设计结构，用于在FBDIMM存储器子系统中使用可变延迟模式来设计，制造和/或测试用于调度数据请求的服务的设计。 调度算法预先计算连接到DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。 返回时间数据表示为在每个向量中一位等于“1”的数据返回时间二进制向量。 对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。 此外，调度算法利用更新的历史向量来确定接收到的请求是否对执行请求产生冲突。 通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。
-
4.发明授权Method for generating reliability tests based on orthogonal arrays and field data 有权基于正交阵列和现场数据生成可靠性测试的方法公开(公告)号：US08019049B2
公开(公告)日：2011-09-13
申请号：US11691665
申请日：2007-03-27
CPC分类号： H04M3/28
摘要： A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.
摘要翻译： 用于产生电话系统的可靠性测试的方法是基于对覆盖测试参数的各种组合的正交阵列的采样进行的。 在电话系统上收集实际电话活动的现场数据。 对现场数据进行评估，以确定呼叫混合特性。 获得不同呼叫混合特性的概率权重，然后使用概率权重来对具有相同呼叫混合特性的正交阵列中生成的测试用例场景进行采样。 这些测试用例场景用于在电话系统上运行测试。 这些测试优选使用自动测试脚本进行。 收集测试数据后，从测试数据计算可靠性度量。
-
公开(公告)号：US08218554B2
公开(公告)日：2012-07-10
申请号：US11875995
申请日：2007-10-22
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.
-
公开(公告)号：US08179897B2
公开(公告)日：2012-05-15
申请号：US11970868
申请日：2008-01-08
IPC分类号： H04L12/28
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.
摘要翻译： 用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC生成器使用2.sup.16位来生成第二个CRC表。 通过将CID字段，LI字段和UUI字段中的位与两个表相关来生成特定CPS头的CRC。
-
公开(公告)号：US08059788B2
公开(公告)日：2011-11-15
申请号：US11769472
申请日：2007-06-27
申请人： James J. Allen, Jr. , Muharrem Umit Uyar , Michael Robert Lundberg , Diane Somers , Shashank Sarwate , William Howard Chriss
发明人： James J. Allen, Jr. , Muharrem Umit Uyar , Michael Robert Lundberg , Diane Somers , Shashank Sarwate , William Howard Chriss
IPC分类号： H04M1/24
CPC分类号： H04M3/22 , H04M3/08 , H04M2203/1016
摘要： The present invention provides a system and method for a computer controlled test system in which the computer can change and monitor the compound observable state of an electronic device or telephone during testing procedure. In the preferred embodiment of the invention, the compound observable state of the electronic device includes a display bit map file or the status of lights or buttons. The compound observable state can be evaluated by the computer in real-time to alert nearby operators of a failure (i.e. a telephone that needs to be rebooted) or malfunction (not rising to the level of a failure). Also, the data related to the compound observable state can be stored in the computer for later review to assist in debugging the telephone's software.
摘要翻译： 本发明提供了一种用于计算机控制测试系统的系统和方法，其中计算机可以在测试过程期间改变和监视电子设备或电话的复合可观察状态。 在本发明的优选实施例中，电子设备的化合物可观察状态包括显示位图文件或灯或按钮的状态。 可以由计算机实时评估复合可观察状态，以向附近的操作员警告故障（即，需要重新启动的电话）或故障（不升到故障水平）。 此外，与复合可观察状态相关的数据可以存储在计算机中以便稍后复查以帮助调试电话的软件。
-
8.发明授权Structure for reducing latency associated with read operations in a memory system 失效用于减少与存储器系统中的读取操作相关联的延迟的结构公开(公告)号：US08140803B2
公开(公告)日：2012-03-20
申请号：US12114787
申请日：2008-05-04
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控制器。 存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线 以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。
-
9.发明授权Apparatus, method and program product to generate and use CRC in communications network 有权在通信网络中生成和使用CRC的装置，方法和程序产品公开(公告)号：US07336667B2
公开(公告)日：2008-02-26
申请号：US10301247
申请日：2002-11-21
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 216 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, Li field and UUI field with the two tables.
摘要翻译： 用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC发生器使用2位16位产生第二个CRC表。 通过将CID字段，Li字段和UUI字段中的比特与两个表相关来生成特定CPS头的CRC。
-
公开(公告)号：US5299196A
公开(公告)日：1994-03-29
申请号：US974654
申请日：1992-11-12
申请人： James J. Allen, Jr.
发明人： James J. Allen, Jr.
IPC分类号： G06F13/12 , G06F13/14 , G06F13/36 , G06F13/364 , G06F13/368 , H04J3/02
CPC分类号： G06F13/364 , G06F13/14
摘要： A method and an apparatus decodes the address of a selected destination user in a time-distributed manner thereby allowing a faster bus cycle and providing earlier error detection. The method and system of the present invention provides for the distribution of the address decoding over two bus cycles, rather than one, so that a faster bus cycle is allowed. In addition, the present invention provides address decode circuitry within the bus arbitrator/controller so that address decoding and error detection can be performed in parallel with bus arbitration.
摘要翻译： 一种方法和装置以时间分布的方式对所选择的目的地用户的地址进行解码，从而允许更快的总线周期并提供较早的错误检测。 本发明的方法和系统提供了在两个总线周期而不是一个总线周期上分配地址解码，使得允许更快的总线周期。 此外，本发明提供总线仲裁器/控制器内的地址解码电路，使得可以与总线仲裁并行执行地址解码和错误检测。
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.031 秒)