公开(公告)号：US07882338B2

公开(公告)日：2011-02-01

申请号：US12034066

申请日：2008-02-20

申请人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito, III ,  Robert J. Sonnelitter, III ,  Charles F. Webb

发明人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito, III ,  Robert J. Sonnelitter, III ,  Charles F. Webb

IPC分类号： G06F9/32

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844

摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.

摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

公开(公告)号：US20090210661A1

公开(公告)日：2009-08-20

申请号：US12034066

申请日：2008-02-20

申请人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  Charles F. Webb

发明人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  Charles F. Webb

IPC分类号： G06F9/312

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844

摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.

摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

公开(公告)号：US07822954B2

公开(公告)日：2010-10-26

申请号：US12034112

申请日：2008-02-20

申请人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

发明人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/383 ,  G06F9/3802 ,  G06F9/3861

摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

摘要翻译： 分支预测算法用于生成是否采用分支的预测。 取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。 执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。 当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

公开(公告)号：US20090210684A1

公开(公告)日：2009-08-20

申请号：US12034112

申请日：2008-02-20

申请人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

发明人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/30

CPC分类号： G06F9/383 ,  G06F9/3802 ,  G06F9/3861

摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

摘要翻译： 分支预测算法用于生成是否采用分支的预测。 取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。 执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。 当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

公开(公告)号：US08443176B2

公开(公告)日：2013-05-14

申请号：US12037042

申请日：2008-02-25

申请人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

发明人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

IPC分类号： G06F9/00

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F12/0862 ,  G06F2212/1021

摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.

摘要翻译： 一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过 基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出 如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。 相应的系统和计算机程序产品。

公开(公告)号：US20090217003A1

公开(公告)日：2009-08-27

申请号：US12037042

申请日：2008-02-25

申请人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

发明人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F12/0862 ,  G06F2212/1021

摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.

摘要翻译： 一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过 基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出 如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。 相应的系统和计算机程序产品。

公开(公告)号：US20090240977A1

公开(公告)日：2009-09-24

申请号：US12051367

申请日：2008-03-19

申请人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

发明人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

IPC分类号： G06F11/14

CPC分类号： G06F11/0751 ,  G06F9/30105 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0721

摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.

摘要翻译： 提供了一种错误检测系统。 该系统包括包括一个或多个数据条目的数据阵列。 复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。 索引生成器选择性地增加引用数据数组的索引。 第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。 误差发生器根据第一个比较器的结果产生一个误差信号。

公开(公告)号：US08176406B2

公开(公告)日：2012-05-08

申请号：US12051367

申请日：2008-03-19

申请人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

发明人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

IPC分类号： G06F7/02

CPC分类号： G06F11/0751 ,  G06F9/30105 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0721

摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.

摘要翻译： 提供了一种错误检测系统。 该系统包括包括一个或多个数据条目的数据阵列。 复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。 索引生成器选择性地增加引用数据数组的索引。 第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。 误差发生器根据第一个比较器的结果产生一个误差信号。

公开(公告)号：US09235419B2

公开(公告)日：2016-01-12

申请号：US13492997

申请日：2012-06-11

申请人： James J. Bonanno ,  Ulrich Mayer ,  Brian R. Prasky

发明人： James J. Bonanno ,  Ulrich Mayer ,  Brian R. Prasky

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3806

摘要： Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.

公开(公告)号：US08909879B2

公开(公告)日：2014-12-09

申请号：US13493644

申请日：2012-06-11

申请人： James J. Bonanno ,  Brian R. Prasky

发明人： James J. Bonanno ,  Brian R. Prasky

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F11/07 ,  G06F12/12

CPC分类号： G06F12/0891 ,  G06F11/076 ,  G06F12/00 ,  G06F12/0802 ,  G06F12/12 ,  G06F13/385

摘要： Embodiments of the invention relate to counter-based entry invalidation for a metadata previous write queue (PWQ). An aspect of the invention includes writing an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline and setting a valid tag associated with the entry in the metadata PWQ to valid. Another aspect of the invention includes initializing a counter to zero and incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold. Yet another aspect of the invention includes setting the valid tag to invalid based on the counter being equal to the threshold.

摘要翻译： 本发明的实施例涉及元数据先前写入队列（PWQ）的基于反向条目的无效。 本发明的一个方面包括将地址写入元数据PWQ中的条目中，该地址与从流水线接收的元数据实例相关联，并且将与元数据PWQ中的条目相关联的有效标签设置为有效。 本发明的另一方面包括：将计数器初始化为零，并基于从流水线接收计数信号递增计数器，直到计数器等于阈值。 本发明的另一方面包括基于等于阈值的计数器将有效标签设置为无效。