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    Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address
    2.
    发明授权
    Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address 失效
    使用多个存储器访问半关联高速缓冲存储器以存储地址的不同组件的方法和结构

    公开(公告)号：US5721863A

    公开(公告)日：1998-02-24

    申请号：US593639

    申请日：1996-01-29

    申请人： James J. Covino ,  Roy Childs Flaker ,  Alan Lee Roberts ,  Jose Roriz Sousa

    发明人： James J. Covino ,  Roy Childs Flaker ,  Alan Lee Roberts ,  Jose Roriz Sousa

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/1054 ,  G06F12/0864

    摘要： A structure and method of operation of a cache memory are provided. The cache memory is organized such that the data on a given line of any page of the main memory is stored on the same line of a page of the cache memory. Two address memories are provided, one containing the first eight bits of the virtual address of the page of the data in main memory and the second the entire real page address in main memory. When an address is asserted on the bus, the line component of the address causes each of those lines from the cache memory to read out to a multiplexor. At the same time, the eight bit component of the virtual address is compared in the first memory to the eight bits of each line stored in the first memory, and if a compare is made, the data on that line from that page of cache memory is read to the CPU. Also, the entire real address is compared in the second memory, and if a match does not occur, the data from the cache to the CPU is flagged as invalid data. A structure and method are also provided to determine if duplicate addresses exist in the second address memory.

    摘要翻译： 提供了高速缓冲存储器的操作结构和操作方法。 高速缓冲存储器被组织使得主存储器的任何页面的给定行上的数据被存储在高速缓冲存储器的页面的同一行上。 提供两个地址存储器，一个包含主存储器中的数据页的虚拟地址的前八位，第二个是主存储器中的整个实际页地址。 当总线上的地址被断言时，地址的线路分量使来自高速缓冲存储器的那些线路中的每条线路读出到多路复用器。 同时，将虚拟地址的八位分量在第一存储器中比较到存储在第一存储器中的每一行的八位，如果进行比较，则从高速缓冲存储器页面那一行的数据 被读取到CPU。 而且，在第二存储器中比较整个实际地址，并且如果不发生匹配，则从缓存到CPU的数据被标记为无效数据。 还提供了一种结构和方法来确定在第二地址存储器中是否存在重复的地址。

    Circuit and methods to improve the operation of SOI devices
    4.
    发明授权
    Circuit and methods to improve the operation of SOI devices 有权
    电路和方法来改善SOI器件的运行

    公开(公告)号：US08093657B2

    公开(公告)日：2012-01-10

    申请号：US12181007

    申请日：2008-07-28

    申请人： Roy Childs Flaker ,  Catherine O'Brien, legal representative ,  Scott Flaker, legal representative ,  Shirley A. Flaker, legal representative ,  Bruce Flaker, legal representative ,  Anne Flaker, legal representative ,  Heather Flaker, legal representative ,  Louis C. Hsu ,  Jente Kuang

    发明人： Roy Childs Flaker ,  Louis C. Hsu ,  Jente Kuang

    IPC分类号： H01L27/13

    CPC分类号： G11C16/08 ,  H01L27/1203

    摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.

    摘要翻译： 根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。 在本发明的优选实施例中，提供了一种脉冲放电电路。 这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。 如上所述，一旦累积的电荷已经消散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。 利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。 或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。 这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。 利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。 各个器件的整体体电阻对器件的电位影响最小。

    Soi-body selective link method and apparatus
    5.
    发明授权
    Soi-body selective link method and apparatus 失效
    单体选择性联动方法及装置

    公开(公告)号：US06410369B1

    公开(公告)日：2002-06-25

    申请号：US09591511

    申请日：2000-06-12

    申请人： Roy Childs Flaker ,  Louis L. Hsu ,  Fariborz Assaderaghi ,  Jack A. Mandelman

    发明人： Roy Childs Flaker ,  Louis L. Hsu ,  Fariborz Assaderaghi ,  Jack A. Mandelman

    IPC分类号： H01L2100

    CPC分类号： H01L27/1104 ,  H01L27/1203

    摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.

    摘要翻译： 绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。 在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。 在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。 最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。