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    Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address
    3.
    发明授权
    Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address 失效
    使用多个存储器访问半关联高速缓冲存储器以存储地址的不同组件的方法和结构

    公开(公告)号：US5721863A

    公开(公告)日：1998-02-24

    申请号：US593639

    申请日：1996-01-29

    申请人： James J. Covino ,  Roy Childs Flaker ,  Alan Lee Roberts ,  Jose Roriz Sousa

    发明人： James J. Covino ,  Roy Childs Flaker ,  Alan Lee Roberts ,  Jose Roriz Sousa

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/1054 ,  G06F12/0864

    摘要： A structure and method of operation of a cache memory are provided. The cache memory is organized such that the data on a given line of any page of the main memory is stored on the same line of a page of the cache memory. Two address memories are provided, one containing the first eight bits of the virtual address of the page of the data in main memory and the second the entire real page address in main memory. When an address is asserted on the bus, the line component of the address causes each of those lines from the cache memory to read out to a multiplexor. At the same time, the eight bit component of the virtual address is compared in the first memory to the eight bits of each line stored in the first memory, and if a compare is made, the data on that line from that page of cache memory is read to the CPU. Also, the entire real address is compared in the second memory, and if a match does not occur, the data from the cache to the CPU is flagged as invalid data. A structure and method are also provided to determine if duplicate addresses exist in the second address memory.

    摘要翻译： 提供了高速缓冲存储器的操作结构和操作方法。 高速缓冲存储器被组织使得主存储器的任何页面的给定行上的数据被存储在高速缓冲存储器的页面的同一行上。 提供两个地址存储器，一个包含主存储器中的数据页的虚拟地址的前八位，第二个是主存储器中的整个实际页地址。 当总线上的地址被断言时，地址的线路分量使来自高速缓冲存储器的那些线路中的每条线路读出到多路复用器。 同时，将虚拟地址的八位分量在第一存储器中比较到存储在第一存储器中的每一行的八位，如果进行比较，则从高速缓冲存储器页面那一行的数据 被读取到CPU。 而且，在第二存储器中比较整个实际地址，并且如果不发生匹配，则从缓存到CPU的数据被标记为无效数据。 还提供了一种结构和方法来确定在第二地址存储器中是否存在重复的地址。

    Using one memory to supply addresses to an associated memory during testing
    4.
    发明授权
    Using one memory to supply addresses to an associated memory during testing 失效
    在测试期间使用一个内存来提供地址给相关的内存

    公开(公告)号：US5563833A

    公开(公告)日：1996-10-08

    申请号：US398465

    申请日：1995-03-03

    申请人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

    发明人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

    IPC分类号： G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/12 ,  G06F12/0893 ,  G11C15/00 ,  G11C8/10 ,  G11C29/10

    摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.

    摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。

    Cycle independent data to echo clock tracking circuit
    5.
    发明授权
    Cycle independent data to echo clock tracking circuit 有权
    循环独立数据到回波时钟跟踪电路

    公开(公告)号：US6134182A

    公开(公告)日：2000-10-17

    申请号：US420694

    申请日：1999-10-19

    申请人： Harold Pilo ,  James J. Covino

    发明人： Harold Pilo ,  James J. Covino

    IPC分类号： G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

    摘要： A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

    摘要翻译： 提供了比较器和可变延迟电路，以在双倍数据速率（DDR）RAM器件中保持数据和回波时钟之间的跟踪。 这是通过提供与实际存储器阵列数据进行跟踪的全局数据信号（虚拟数据信号）来实现的。 将该全局数据信号与RAM时钟（CLOCK）的定时进行比较，以确定必须延迟流水线时钟（CLKRISE / CLKFALL）的两个之间的延迟时间。 结果，流水线时钟根据需要被推出，使得它们总是在阵列数据到达输出锁存器之后转换。 因此，随着周期时间的减​​少，回波时钟和数据都被相同地推出并保持其所需的跟踪。

    DRAM-based separate I/O memory solution for communication applications
    6.
    发明授权
    DRAM-based separate I/O memory solution for communication applications 有权
    基于DRAM的单独I / O存储器解决方案，用于通信应用

    公开(公告)号：US06854041B2

    公开(公告)日：2005-02-08

    申请号：US10065839

    申请日：2002-11-25

    申请人： James J. Covino ,  Kevin G. Petrunich ,  Harold Pilo

    发明人： James J. Covino ,  Kevin G. Petrunich ,  Harold Pilo

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C11/409 ,  G06F13/14

    CPC分类号： G11C11/40618 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/406 ,  G11C11/409

    摘要： A structure and method for performing back-to-back read and write memory operations to a same DRAM bank comprising articulating between reading data on a first bank during successive first bank read cycles and writing data to a second bank during successive second bank write cycles, cycling between reading data on the second bank during successive second bank read cycles and writing data to the first bank during successive first bank write cycles, and performing a refresh cycle on the first and second bank, wherein the first bank write cycles lag the first bank read cycles, and wherein the second bank write cycles lag the second bank read cycles. Moreover, the read and write memory operations constantly swap between the read and write cycles and between the first and second bank.

    摘要翻译： 一种用于对同一DRAM组执行背靠背读和写存储器操作的结构和方法，包括在连续的第一存储体读周期期间在第一存储体上读取数据和在连续的第二存储体写周期期间将数据写入第二存储体的关系， 在连续的第二组读取周期期间在第二组上的读取数据之间循环，并且在连续的第一组写周期期间将数据写入第一组，并且在第一和第二组上执行刷新周期，其中第一组写入周期落后于第一组 读周期，并且其中第二存储体写周期滞后于第二存储体读周期。 此外，读和写存储器操作在读和写周期之间以及第一和第二存储体之间不断地交换。

    Efficient semiconductor burn-in circuit and method of operation
    7.
    发明授权
    Efficient semiconductor burn-in circuit and method of operation 失效
    高效半导体老化电路及其操作方法

    公开(公告)号：US6038181A

    公开(公告)日：2000-03-14

    申请号：US136112

    申请日：1998-08-18

    申请人： George M. Braceras ,  James J. Covino ,  Richard E. Hee ,  Harold Pilo

    发明人： George M. Braceras ,  James J. Covino ,  Richard E. Hee ,  Harold Pilo

    IPC分类号： G11C29/00 ,  G01R31/30 ,  G11C7/00

    CPC分类号： G01R31/30

    摘要： The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.

    摘要翻译： 所公开的发明提供了一种提高老化测试速度的半导体器件的电路和老化测试方法。 本发明通过在每个功率循环期间使被测设备中的每一个被测试多次（从2到32倍）来实现。 通过被测单元的这种多次循环，在电源循环期间，总测试时间缩短。 还已经发现，根据本发明测试的装置被更有效地应力并且具有比通过现有技术测试的装置更大的可靠性。 根据本发明，被测试的存储器或逻辑器件设置有相应的时钟装置，其将在每个功率循环期间通过多次（从2到32+倍）的写入和读取操作来操作被测试的每个器件。 如果在读取操作期间记录任何失败，则提供每个读取操作的数据一致性。 因此，本发明提供了一种老化测试，其更有效地将半导体器件（例如存储器或逻辑单元）应力高达32倍。本发明通过在半导体器件的周期内循环该时钟x次来利用半导体器件的内部时钟 在老化测试中每个外部时钟周期的周期，同时使这些内部周期与测试周期同步，从而为每个内部循环提供相干数据。

    Folded dummy world line
    8.
    发明授权
    Folded dummy world line 失效
    折叠虚拟世界线

    公开(公告)号：US5841720A

    公开(公告)日：1998-11-24

    申请号：US918740

    申请日：1997-08-26

    申请人： James J. Covino ,  Alan L. Roberts ,  Jose R. Sousa

    发明人： James J. Covino ,  Alan L. Roberts ,  Jose R. Sousa

    IPC分类号： G11C11/413 ,  G11C7/14 ,  G11C8/18 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C7/02

    CPC分类号： G11C8/18 ,  G11C7/14

    摘要： A memory array comprising a number of memory cells, a set path, a signal path, and at least one word line for transmitting a word line select signal to a row of the memory cells. The word line extends from a first driver end to a second end. The memory array further includes a dummy word line extending from the first driver end to a point between the first and second ends and back to the first end for transmitting a tracking signal responsive to the word line select signal. By folding the dummy word line in this manner, improved tracking of the set path with the signal path is achieved.

    摘要翻译： 一种存储器阵列，包括多个存储器单元，设定路径，信号路径以及用于将字线选择信号发送到存储器单元的行的至少一个字线。 字线从第一驱动器端延伸到第二端。 存储器阵列还包括从第一驱动器端延伸到第一端和第二端之间的点并返回到第一端的虚拟字线，用于响应于字线选择信号发送跟踪信号。 通过以这种方式折叠伪字线，实现了具有信号路径的设定路径的改进跟踪。

    Dynamic CMOS circuits with noise immunity
    9.
    发明授权
    Dynamic CMOS circuits with noise immunity 失效
    动态CMOS电路具有抗噪声能力

    公开(公告)号：US5650733A

    公开(公告)日：1997-07-22

    申请号：US547269

    申请日：1995-10-24

    申请人： James J. Covino

    发明人： James J. Covino

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K17/693 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/096

    CPC分类号： H03K19/0963 ,  H03K17/693 ,  H03K19/00361

    摘要： Dynamic CMOS circuits are provided with improved noise immunity. These circuits comprise first and second stacked NFET devices connected respectively between ground and a first node. An input node is coupled to the first NFET device closest to ground and a clock node coupled to the second NFET device closest to the first node. A PFET device is connected between the input node and a node formed by the stacked NFET devices. The first NFET device and the PFET device form an inverter for receiving an input signal, the switch point of the inverter being adjustable by adjusting the PFET/NFET ratio of the inverter, thereby increasing the noise immunity of the circuit.

    摘要翻译： 动态CMOS电路具有改进的抗噪声能力。 这些电路包括分别连接在地和第一节点之间的第一和第二叠层NFET器件。 输入节点耦合到最靠近地的第一NFET器件，以及耦合到最靠近第一节点的第二NFET器件的时钟节点。 PFET器件连接在输入节点和由堆叠的NFET器件形成的节点之间。 第一NFET器件和PFET器件形成用于接收输入信号的反相器，通过调节逆变器的PFET / NFET比可以调节反相器的开关点，从而提高电路的抗噪声能力。

    Method and apparatus for testing redundant word and bit lines in a memory array
    10.
    发明授权
    Method and apparatus for testing redundant word and bit lines in a memory array 失效
    用于测试存储器阵列中的冗余字和位线的方法和装置

    公开(公告)号：US5631868A

    公开(公告)日：1997-05-20

    申请号：US563831

    申请日：1995-11-28

    申请人： Luigi Termullo, Jr. ,  Marcel J. Robillard ,  James J. Covino ,  Stuart J. Hall

    发明人： Luigi Termullo, Jr. ,  Marcel J. Robillard ,  James J. Covino ,  Stuart J. Hall

    IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C7/00 ,  G01R31/28

    CPC分类号： G11C29/838 ,  G11C29/24

    摘要： A method and apparatus for evaluating a memory having memory elements and redundant memory elements for redundancy replacement. The redundant memory elements are tested to determine the number of good redundant memory elements. The memory elements are also tested to determine whether there are any failing memory elements. It is then determined whether a sufficient number of good redundant elements are available to replace the failing memory elements. If an insufficient number of redundant memory elements are available, the testing is stopped.

    摘要翻译： 一种用于评估具有存储元件的存储器和用于冗余替换的冗余存储器元件的方法和装置。 测试冗余存储器元件以确定良好冗余存储器元件的数量。 还测试存储器元件以确定是否存在任何故障存储器元件。 然后确定足够数量的良好冗余元件是否可用于替换故障存储器元件。 如果冗余内存元素数量不足，则会停止测试。