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公开(公告)号：US09053031B2
公开(公告)日：2015-06-09
申请号：US11953201
申请日：2007-12-10
申请人： James Johnson Allen, Jr. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, Jr. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
CPC分类号： G06F12/0862
摘要： A method for handling speculative access requests for a storage device in a computer system is provided. The method includes the steps of providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to be speculatively issued, and intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. In another embodiment, a method for reducing data access latency experienced by a user in a computer network is provided. The method includes the steps of providing a web page comprising a link to a data file stored on a database connected to the computer network, selecting a speculative access threshold corresponding to a selected percentage of data accesses which are to be speculatively provided to the user, and speculatively providing the data file in accordance with the speculative access threshold.
摘要翻译： 提供了一种用于处理计算机系统中的存储设备的推测访问请求的方法。 该方法包括以下步骤：提供与被推测发布的总访问次数的选定百分比相对应的推测访问阈值，以及根据推测访问阈值混合请求访问和推测访问。 在另一个实施例中，提供了一种用于减少用户在计算机网络中经历的数据访问延迟的方法。 该方法包括以下步骤：提供网页，其包括链接到存储在连接到计算机网络的数据库上的数据文件的链接，选择与要推测性地提供给用户的所选百分比的数据访问相对应的推测访问阈值， 并根据推测访问阈值推测提供数据文件。
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公开(公告)号：US20090150622A1
公开(公告)日：2009-06-11
申请号：US11953255
申请日：2007-12-10
申请人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F2212/507
摘要： A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold.
摘要翻译： 提供了一种用于处理计算机系统中的存储器控制器的推测读请求的系统和方法。 在一个示例中，一种方法包括以下步骤：提供与可推测性地发布的总读数的选定百分比相对应的推测读取阈值，以及根据推测读取阈值混合需求读取和推测性读取。 在另一示例中，计算机系统包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供对应于可以推测地读取总数的所选百分比的推测读取阈值的电路 以及根据推测性读取阈值来混合需求读取和推测性读取的电路。 在另一示例中，一种方法包括以下步骤：提供与搜索计算机系统的高速缓存所需的时间段的选定百分比相对应的推测性调度时间阈值，以及根据投机调度时间混合需求读取和推测读取 阈。
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公开(公告)号：US07949830B2
公开(公告)日：2011-05-24
申请号：US11953255
申请日：2007-12-10
申请人： James Johnson Allen, Jr. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, Jr. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
CPC分类号： G06F12/0806 , G06F2212/507
摘要： A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold.
摘要翻译： 提供了一种用于处理计算机系统中的存储器控制器的推测读请求的系统和方法。 在一个示例中，一种方法包括以下步骤：提供与可推测性地发布的总读数的选定百分比相对应的推测读取阈值，以及根据推测读取阈值混合需求读取和推测性读取。 在另一示例中，计算机系统包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供对应于可以推测地读取总数的所选百分比的推测读取阈值的电路 以及根据推测性读取阈值来混合需求读取和推测性读取的电路。 在另一示例中，一种方法包括以下步骤：提供与搜索计算机系统的高速缓存所需的时间段的选定百分比相对应的推测性调度时间阈值，以及根据投机调度时间混合需求读取和推测读取 阈。
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公开(公告)号：US20090150401A1
公开(公告)日：2009-06-11
申请号：US11953201
申请日：2007-12-10
申请人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
发明人： James Johnson Allen, JR. , Steven Kenneth Jenkins , James A. Mossman , Michael Raymond Trombley
CPC分类号： G06F12/0862
摘要： A method for handling speculative access requests for a storage device in a computer system is provided. The method includes the steps of providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to be speculatively issued, and intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. In another embodiment, a method for reducing data access latency experienced by a user in a computer network is provided. The method includes the steps of providing a web page comprising a link to a data file stored on a database connected to the computer network, selecting a speculative access threshold corresponding to a selected percentage of data accesses which are to be speculatively provided to the user, and speculatively providing the data file in accordance with the speculative access threshold.
摘要翻译： 提供了一种用于处理计算机系统中的存储设备的推测访问请求的方法。 该方法包括以下步骤：提供与被推测发布的总访问次数的选定百分比相对应的推测访问阈值，以及根据推测访问阈值混合请求访问和推测访问。 在另一个实施例中，提供了一种用于减少用户在计算机网络中经历的数据访问延迟的方法。 该方法包括以下步骤：提供网页，其包括链接到存储在连接到计算机网络的数据库上的数据文件的链接，选择与要推测性地提供给用户的所选百分比的数据访问相对应的推测访问阈值， 并根据推测访问阈值推测提供数据文件。
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公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US08284621B2
公开(公告)日：2012-10-09
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C8/18
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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7.发明授权Structure for reducing latency associated with read operations in a memory system 失效用于减少与存储器系统中的读取操作相关联的延迟的结构公开(公告)号：US08140803B2
公开(公告)日：2012-03-20
申请号：US12114787
申请日：2008-05-04
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控制器。 存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线 以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。
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公开(公告)号：US08032713B2
公开(公告)日：2011-10-04
申请号：US12115146
申请日：2008-05-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路 根据投机访问阈值访问和推测访问。
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公开(公告)号：US20110234259A1
公开(公告)日：2011-09-29
申请号：US12729455
申请日：2010-03-23
申请人： Theodore P. Haggis , Robert B. Likovich, JR. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
发明人： Theodore P. Haggis , Robert B. Likovich, JR. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
IPC分类号： H03K19/0175
CPC分类号： G06F13/4243
摘要： A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.
摘要翻译： 一种总线系统，其包括耦合到公共信号总线的多个信号驱动装置，耦合到公共信号总线的总线控制电路和比较电路。 多个信号驱动装置包括第一信号驱动装置和第二信号驱动装置。 总线控制器包括具有用于每个信号驱动装置的可配置延迟的延迟补偿电路。 延迟补偿电路具有与第一信号驱动装置相关联的电流延迟链配置。 比较电路被配置为将与第一信号驱动装置相关联的第一可配置延迟与与多个信号驱动装置中的第二信号驱动装置相关联的第二可配置延迟进行比较，并且用于响应于比较来产生响应于指示是否 当前延迟链配置可以由第二信号驱动装置使用。
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公开(公告)号：US07937533B2
公开(公告)日：2011-05-03
申请号：US12114792
申请日：2008-05-04
CPC分类号： G06F12/0815 , G06F2212/507
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供与可读取总数的所选百分比相对应的推测读取阈值的电路 推测性发布，以及根据推测读取阈值混合需求读取和推测读取的电路。
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