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    Three-terminal non-volatile memory element with hybrid gate dielectric
    1.
    发明授权
    Three-terminal non-volatile memory element with hybrid gate dielectric 有权
    具有混合栅极电介质的三端非易失性存储元件

    公开(公告)号：US07687797B1

    公开(公告)日：2010-03-30

    申请号：US11210500

    申请日：2005-08-24

    申请人： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

    发明人： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

    IPC分类号： H01L29/06 ,  H01L47/02

    CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

    摘要： A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

    摘要翻译： MOS晶体管用作可编程三端非易失性存储元件。 MOS晶体管的栅介质层具有比第二部分具有相对更高的介电击穿强度的第一部分。 选择第二部分的位置以避免在编程期间栅极电介质层在有源区域或隔离区域的边缘附近分解。 在特定实施例中，栅介质层是氧化硅，第一部分比第二部分厚。

    Method of programming a three-terminal non-volatile memory element using source-drain bias
    2.
    发明授权
    Method of programming a three-terminal non-volatile memory element using source-drain bias 有权
    使用源极 - 漏极偏置来编程三端非易失性存储元件的方法

    公开(公告)号：US07420842B1

    公开(公告)日：2008-09-02

    申请号：US11210595

    申请日：2005-08-24

    申请人： Michael G. Ahrens ,  Shahin Toutounchi ,  James Karp ,  Jongheon Jeong

    发明人： Michael G. Ahrens ,  Shahin Toutounchi ,  James Karp ,  Jongheon Jeong

    IPC分类号： G11C11/34

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

    摘要翻译： 存储晶体管通过在将编程电压施加到栅极的情况下偏置源极和漏极而被编程为非易失性存储器元件。 基板保持在与源极/漏极不同的电位，以确保在编程步骤期间在沟道区域和栅极之间而不是栅极和源极/漏极发生最大的电压差。 编程电压加热通道区域，以在源极和漏极之间形成非易失性低电阻连接，读取该电阻以确定编程状态。

    PMOS three-terminal non-volatile memory element and method of programming
    4.
    发明授权
    PMOS three-terminal non-volatile memory element and method of programming 有权
    PMOS三端非易失性存储元件及编程方法

    公开(公告)号：US07450431B1

    公开(公告)日：2008-11-11

    申请号：US11210496

    申请日：2005-08-24

    申请人： James Karp ,  Jongheon Jeong ,  Michael G. Ahrens ,  Shahin Toutounchi

    发明人： James Karp ,  Jongheon Jeong ,  Michael G. Ahrens ,  Shahin Toutounchi

    IPC分类号： G11C16/04

    CPC分类号： G11C17/16

    摘要： A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

    摘要翻译： 通过在累积模式下操作PMOS晶体管，将PMOS晶体管编程为非易失性存储元件。 这有助于将源极和漏极区域合并以形成低电阻路径，因为大多数加热发生在栅极电介质的沟道侧，而不是栅极端子侧。 在一个具体实施方案中，使用硼作为掺杂剂。 硼具有比砷或磷更高的扩散性，它们是典型的n型掺杂剂。 硼的较高扩散性促进了源区和漏区的融合。

    Non-volatile memory array using gate breakdown structures
    6.
    发明授权
    Non-volatile memory array using gate breakdown structures 有权
    使用门击穿结构的非易失性存储器阵列

    公开(公告)号：US06522582B1

    公开(公告)日：2003-02-18

    申请号：US09553571

    申请日：2000-04-19

    申请人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

    发明人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

    IPC分类号： G11C1400

    CPC分类号： G11C16/08

    摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

    摘要翻译： 描述了用于非易失性存储器件的存储单元结构和相关电路。 可以使用标准CMOS工艺制造电池结构，例如 次0.35微米或次级0.25微米工艺。 优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。 有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。 例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径 型源极/漏极区域。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。 此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。 这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

    Three terminal non-volatile memory element
    8.
    发明授权
    Three terminal non-volatile memory element 有权
    三端非易失性存储元件

    公开(公告)号：US06266269B1

    公开(公告)日：2001-07-24

    申请号：US09589337

    申请日：2000-06-07

    申请人： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi

    发明人： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi

    IPC分类号： G11C1124

    CPC分类号： G11C16/0466

    摘要： A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.

    摘要翻译： 三端非易失性存储元件包括标准（低电压）CMOS晶体管，即存储晶体管，其具有耦合到读位线的漏极和连接到地的源极。 存储晶体管通过向其栅极施加高编程电压来编程，从而破坏存储晶体管的栅极氧化物。 重要的是，在亚微米技术中，存储晶体管的源极和漏极区域合并，从而提供高度可靠的导电路径。 因此，存储单元的状态可以有利地仅通过读位线读取。

    Method of forming a zener diode
    9.
    发明授权
    Method of forming a zener diode 有权
    形成齐纳二极管的方法

    公开(公告)号：US06645802B1

    公开(公告)日：2003-11-11

    申请号：US09877690

    申请日：2001-06-08

    申请人： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

    发明人： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

    IPC分类号： H01L218234

    CPC分类号： H01L27/0251 ,  Y10S438/983

    摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

    摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。 电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。 齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。 如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。 齐纳二极管包括阳极和阴极扩散。 阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。 阳极扩散通过阴极扩散向下延伸到半导体衬底中。 阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。 可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

    Electrostatic-discharge protection circuit
    10.
    发明授权
    Electrostatic-discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US06268639B1

    公开(公告)日：2001-07-31

    申请号：US09248547

    申请日：1999-02-11

    申请人： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

    发明人： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

    IPC分类号： H01L218222

    CPC分类号： H01L27/0251 ,  Y10S438/983

    摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

    摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。 电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。 齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。 如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。 齐纳二极管包括阳极和阴极扩散。 阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。 阳极扩散通过阴极扩散向下延伸到半导体衬底中。 阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。 可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。