公开(公告)号：US07687797B1

公开(公告)日：2010-03-30

申请号：US11210500

申请日：2005-08-24

Applicant: James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

Inventor： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

IPC: H01L29/06 ,  H01L47/02

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Abstract translation: MOS晶体管用作可编程三端非易失性存储元件。 MOS晶体管的栅介质层具有比第二部分具有相对更高的介电击穿强度的第一部分。 选择第二部分的位置以避免在编程期间栅极电介质层在有源区域或隔离区域的边缘附近分解。 在特定实施例中，栅介质层是氧化硅，第一部分比第二部分厚。

公开(公告)号：US06549458B1

公开(公告)日：2003-04-15

申请号：US10040044

申请日：2001-10-25

Applicant: Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

Inventor： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC: G11C1400

CPC classification number: G11C16/08

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract translation: 用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。 有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

公开(公告)号：US06522582B1

公开(公告)日：2003-02-18

申请号：US09553571

申请日：2000-04-19

Applicant: Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

Inventor： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC: G11C1400

CPC classification number: G11C16/08

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

Abstract translation: 描述了用于非易失性存储器件的存储单元结构和相关电路。 可以使用标准CMOS工艺制造电池结构，例如 次0.35微米或次级0.25微米工艺。 优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。 有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。 例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径 型源极/漏极区域。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。 此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。 这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

公开(公告)号：US06266269B1

公开(公告)日：2001-07-24

申请号：US09589337

申请日：2000-06-07

Applicant: James Karp ,  Daniel Gitlin ,  Shahin Toutounchi

Inventor： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi

IPC: G11C1124

CPC classification number: G11C16/0466

Abstract: A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.

Abstract translation: 三端非易失性存储元件包括标准（低电压）CMOS晶体管，即存储晶体管，其具有耦合到读位线的漏极和连接到地的源极。 存储晶体管通过向其栅极施加高编程电压来编程，从而破坏存储晶体管的栅极氧化物。 重要的是，在亚微米技术中，存储晶体管的源极和漏极区域合并，从而提供高度可靠的导电路径。 因此，存储单元的状态可以有利地仅通过读位线读取。

公开(公告)号：US06268639B1

公开(公告)日：2001-07-31

申请号：US09248547

申请日：1999-02-11

Applicant: Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

Inventor： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

IPC: H01L218222

CPC classification number: H01L27/0251 ,  Y10S438/983

Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

Abstract translation: ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。 电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。 齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。 如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。 齐纳二极管包括阳极和阴极扩散。 阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。 阳极扩散通过阴极扩散向下延伸到半导体衬底中。 阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。 可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

公开(公告)号：US06645802B1

公开(公告)日：2003-11-11

申请号：US09877690

申请日：2001-06-08

Applicant: Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

Inventor： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

IPC: H01L218234

CPC classification number: H01L27/0251 ,  Y10S438/983

Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

Abstract translation: ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。 电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。 齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。 如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。 齐纳二极管包括阳极和阴极扩散。 阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。 阳极扩散通过阴极扩散向下延伸到半导体衬底中。 阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。 可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

公开(公告)号：US06740936B1

公开(公告)日：2004-05-25

申请号：US10134086

申请日：2002-04-25

Applicant: Daniel Gitlin ,  James Karp ,  Jongheon Jeong ,  Jan L. de Jong

Inventor： Daniel Gitlin ,  James Karp ,  Jongheon Jeong ,  Jan L. de Jong

IPC: H01L2978

CPC classification number: H01L29/8605

Abstract: A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Abstract translation: 形成在晶体管漏极和漏极接触之间的具有镇流电阻的晶体管由镇流电阻器的掩蔽区域形成，以增加电阻率，从而减少所需面积。 本发明实现了这一点，而不引入任何附加的处理或掩蔽步骤。 因此，本发明允许针对相同ESD要求降低IC管芯尺寸，或者允许针对给定裸片尺寸的更好的ESD保护。

公开(公告)号：US20110267103A1

公开(公告)日：2011-11-03

申请号：US13127473

申请日：2009-01-07

Applicant: Daniel Gitlin ,  Martin Voogel ,  Jason Redgrave ,  Matt Crowley

Inventor： Daniel Gitlin ,  Martin Voogel ,  Jason Redgrave ,  Matt Crowley

IPC: H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/017509 ,  H03K19/17704 ,  H03K19/17784

Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Abstract translation: 一些实施例提供集成电路（'IC'），其包括以第一电压工作的至少第一和第二电路。 IC包括在第一和第二电路之间的直接连接，其包括用于以低于第一电压的第二电压将信号从第一电路传输到第二电路的第三电路。 第一和第二电路中的至少一个是用于可配置地执行操作的可配置电路。

公开(公告)号：US07839693B1

公开(公告)日：2010-11-23

申请号：US12683585

申请日：2010-01-07

Applicant: Sunhom Paak ,  Boon Y. Ang ,  Hsung J. Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Y. Ang ,  Hsung J. Im ,  Daniel Gitlin

IPC: G11C16/06

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US06621325B2

公开(公告)日：2003-09-16

申请号：US09956203

申请日：2001-09-18

Applicant: Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

Inventor： Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

IPC: H03K301

CPC classification number: H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract translation: 用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。 用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。 在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。 在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。