公开(公告)号：US08569130B2

公开(公告)日：2013-10-29

申请号：US13192763

申请日：2011-07-28

申请人： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

发明人： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

摘要： Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.

摘要翻译： 公开了在如此形成的具有气隙的存储器阵列和存储器阵列中形成气隙的方法。 一种这样的方法可以包括通过半导体上的电荷存储结构形成具有第一电介质的隔离区域，所述隔离区域延伸到半导体中; 在隔离区域和电荷存储结构上形成第二电介质; 并且在隔离区域中形成气隙，使得气隙通过电荷存储结构，并且第一电介质的厚度在气隙和第二电介质之间。

公开(公告)号：US20130168756A1

公开(公告)日：2013-07-04

申请号：US13343087

申请日：2012-01-04

申请人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

发明人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

摘要： Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

摘要翻译： 公开了设备，存储器阵列和方法。 在一个实施例中，一个这样的器件具有源极/漏极区域，其具有第一和第二有源区域，以及在第一和第二有源区域之间的隔离区域和电介质插塞。 电介质插塞可以延伸到第一和第二有源区域的上表面之下，并且可以由对于特定各向同性去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US08907396B2

公开(公告)日：2014-12-09

申请号：US13343087

申请日：2012-01-04

申请人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

发明人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

摘要： Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

摘要翻译： 公开了设备，存储器阵列和方法。 在一个实施例中，一个这样的器件具有源极/漏极区域，其具有第一和第二有源区域，以及在第一和第二有源区域之间的隔离区域和电介质插塞。 电介质插塞可以延伸到第一和第二有源区域的上表面之下，并且可以由对于特定各向同性去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US08034706B2

公开(公告)日：2011-10-11

申请号：US12787684

申请日：2010-05-26

申请人： James Mathew ,  H. Montgomery Manning

发明人： James Mathew ,  H. Montgomery Manning

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material.

摘要翻译： 本公开包括各种接触实施方式。 一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中产生沟槽，并且具有位于多个栅极之间的沟槽的一部分。 该方法包括在沟槽中沉积填充材料并将填充材料蚀刻到小于绝缘体堆叠材料的特定厚度的特定深度。 该方法还包括将间隔物材料沉积到沟槽的至少一个侧表面至填充材料的特定深度，并将导电材料沉积在填料材料上的沟槽中。

公开(公告)号：US08461016B2

公开(公告)日：2013-06-11

申请号：US13268066

申请日：2011-10-07

申请人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

发明人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC分类号： H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

摘要： A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

摘要翻译： 形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。 电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。 电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积 处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。 公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

公开(公告)号：US20070202677A1

公开(公告)日：2007-08-30

申请号：US11363661

申请日：2006-02-27

申请人： James Mathew ,  H. Manning

发明人： James Mathew ,  H. Manning

IPC分类号： H01L21/44

CPC分类号： H01L21/76804 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.

摘要翻译： 本公开包括各种方法，电路，设备和系统实施例。 一种这样的方法实施例包括在绝缘体堆叠材料中形成沟槽，其具有位于多个栅极中的两个之间的沟槽的一部分，并且将间隔物材料沉积到沟槽的至少一个侧表面。 该方法还包括将导电材料沉积到沟槽中并将盖材料沉积到沟槽中。

公开(公告)号：US08377819B2

公开(公告)日：2013-02-19

申请号：US13237126

申请日：2011-09-20

申请人： James Mathew ,  H. Montgomery Manning

发明人： James Mathew ,  H. Montgomery Manning

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material.

摘要翻译： 本公开包括各种接触实施方式。 一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中形成沟槽。 该方法包括在沟槽中形成填充材料，并将填料材料移除到小于绝缘体堆叠材料的特定厚度的特定深度。 该方法还包括在沟槽的至少一个侧表面上形成隔离材料至填充材料的特定深度，并在填充材料上的沟槽中形成导电材料。

公开(公告)号：US20130087883A1

公开(公告)日：2013-04-11

申请号：US13268066

申请日：2011-10-07

申请人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

发明人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC分类号： H01L29/06 ,  H01L21/31

CPC分类号： H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

摘要： A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

摘要翻译： 形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。 电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。 电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积 处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。 公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

公开(公告)号：US20120009779A1

公开(公告)日：2012-01-12

申请号：US13237126

申请日：2011-09-20

申请人： James Mathew ,  H. Montgomery Manning

发明人： James Mathew ,  H. Montgomery Manning

IPC分类号： H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material.

摘要翻译： 本公开包括各种接触实施方式。 一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中形成沟槽。 该方法包括在沟槽中形成填充材料，并将填料材料移除到小于绝缘体堆叠材料的特定厚度的特定深度。 该方法还包括在沟槽的至少一个侧表面上形成隔离材料至填充材料的特定深度，并在填充材料上的沟槽中形成导电材料。

公开(公告)号：US20100233875A1

公开(公告)日：2010-09-16

申请号：US12787684

申请日：2010-05-26

申请人： James Mathew ,  H. Montgomery Manning

发明人： James Mathew ,  H. Montgomery Manning

IPC分类号： H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material.

摘要翻译： 本公开包括各种接触实施方式。 一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中产生沟槽，并且具有位于多个栅极之间的沟槽的一部分。 该方法包括在沟槽中沉积填充材料并将填充材料蚀刻到小于绝缘体堆叠材料的特定厚度的特定深度。 该方法还包括将间隔物材料沉积到沟槽的至少一个侧表面至填充材料的特定深度，并将导电材料沉积在填料材料上的沟槽中。