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    Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor
    1.
    发明授权
    Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor 失效
    方法随机或伪随机，无偏差，选择微处理器性能分析指令

    公开(公告)号：US07620801B2

    公开(公告)日：2009-11-17

    申请号：US11055848

    申请日：2005-02-11

    申请人： James Wilson Bishop ,  Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Dung Quoc Nguyen ,  Philip Lee Vitale

    发明人： James Wilson Bishop ,  Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Dung Quoc Nguyen ,  Philip Lee Vitale

    IPC分类号： G06F9/30

    CPC分类号： G06F11/3409 ,  G06F11/3466 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    摘要： A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.

    摘要翻译： 一种用于伪随机，无偏差的方法，用于在微处理器中选择用于标记的指令。 响应于从指令高速缓存读取指令，将与指令相关联的指令标记与线性反馈移位寄存器（LFSR）中的伪随机生成值进行比较。 如果指令标签与LFSR中的值相匹配，则表示指令是标记指令的标记位与指令一起发送到执行单元。 响应于性能监视器的指示，LFSR中的值在选择下一个要标记的指令之前递增。 如果该值等于预定的素数增量，则该值被重置为全部值，以避免与正在执行的码流的任何谐波。 在接收到标记指令之后，执行单元将所标记的位与所选择的事件相结合，并将标记的事件报告给性能监视器。

    Method of seamlessly integrating thermal event information data with performance monitor data
    2.
    发明授权
    Method of seamlessly integrating thermal event information data with performance monitor data 有权
    将热事件信息数据与性能监视数据无缝集成的方法

    公开(公告)号：US07472315B2

    公开(公告)日：2008-12-30

    申请号：US11054292

    申请日：2005-02-09

    申请人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    发明人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    IPC分类号： G06F11/00

    CPC分类号： G06F11/00

    摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.

    摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

    Apparatus, system and computer program product for seamlessly integrating thermal event information data with performance monitor data
    3.
    发明授权
    Apparatus, system and computer program product for seamlessly integrating thermal event information data with performance monitor data 失效
    用于将热事件信息数据与性能监视数据无缝集成的装置，系统和计算机程序产品

    公开(公告)号：US07711994B2

    公开(公告)日：2010-05-04

    申请号：US12131070

    申请日：2008-05-31

    申请人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    发明人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    IPC分类号： G06F11/00

    CPC分类号： G06F11/00

    摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.

    摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

    APPARATUS, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SEAMLESSLY INTEGRATING THERMAL EVENT INFORMATION DATA WITH PERFORMANCE MONITOR DATA
    4.
    发明申请
    APPARATUS, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SEAMLESSLY INTEGRATING THERMAL EVENT INFORMATION DATA WITH PERFORMANCE MONITOR DATA 失效
    装置，系统和计算机程序产品，用于无缝集成具有性能监视数据的热事件信息数据

    公开(公告)号：US20080244330A1

    公开(公告)日：2008-10-02

    申请号：US12131070

    申请日：2008-05-31

    申请人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    发明人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    IPC分类号： G06F11/30

    CPC分类号： G06F11/00

    摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.

    摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

    Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters
    5.
    发明授权
    Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters 失效
    使用多个分配的计数器计数指令表的等待时间，刷新，补充和指令执行

    公开(公告)号：US06970999B2

    公开(公告)日：2005-11-29

    申请号：US10210415

    申请日：2002-07-31

    申请人： Toshihiko Kurihara ,  Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Hideki Mitsubayashi ,  Michitaka Okuno ,  Masahiro Tokoro

    发明人： Toshihiko Kurihara ,  Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Hideki Mitsubayashi ,  Michitaka Okuno ,  Masahiro Tokoro

    IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855

    摘要： A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.

    摘要翻译： 一种用于分析处理器中每条指令（CPI）性能的循环的方法和系统。 完成表对应于要由处理器处理的组中的指令。 一个空的完成表表明有一些类型的灾难导致表冲洗。 当表为空时，位于处理器中的性能监视单元（PMU）中的性能监视计数器（PMC）会计数表为空的时钟周期数。 优选地，根据完成表为空的原因，使用单独的PMC。 第二个PMC同样计算重新填充空完成表的时钟周期数。 第三个PMC计算在完成表中实际执行指令花费的时钟周期数。 PMC中的信息可用于评估CPI性能下降的真正原因。

    Analyzing instruction completion delays in a processor
    7.
    发明授权
    Analyzing instruction completion delays in a processor 失效
    分析处理器中的指令完成延迟

    公开(公告)号：US07047398B2

    公开(公告)日：2006-05-16

    申请号：US10210358

    申请日：2002-07-31

    申请人： Toshihiko Kurihara ,  Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Michitaka Okuno ,  Masahiro Tokoro

    发明人： Toshihiko Kurihara ,  Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Michitaka Okuno ,  Masahiro Tokoro

    IPC分类号： G06F11/34

    CPC分类号： G06F11/348 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F11/3466 ,  G06F2201/88

    摘要： A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.

    摘要翻译： 一种用于识别计算机处理器中的一组指令的指令完成延迟的方法和系统。 指令组中的每个指令都有一个状态指示器，用于标识阻止该指令完成执行的内容。 完成延迟的示例是缓存未命中，数据依赖性或简单地计算机处理器中的执行单元处理指令所需的时间。 每个指令执行完毕后，相关状态指示灯将被清除，表示该指令不再等待执行。 执行的最后一条指令是保持整个组的完成的指令，因此将最后指令的完成延迟的原因记录为整个组的完成延迟的原因。

    Method and apparatus for identifying instructions for performance monitoring in a microprocessor
    9.
    发明授权
    Method and apparatus for identifying instructions for performance monitoring in a microprocessor 失效
    用于识别用于微处理器中的性能监视的指令的方法和装置

    公开(公告)号：US06539502B1

    公开(公告)日：2003-03-25

    申请号：US09436109

    申请日：1999-11-08

    申请人： Joel Roger Davidson ,  Michael Stephen Floyd ,  Judith E. K. Laurens ,  Alexander Erik Mericas

    发明人： Joel Roger Davidson ,  Michael Stephen Floyd ,  Judith E. K. Laurens ,  Alexander Erik Mericas

    IPC分类号： G06F1130

    CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/88

    摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V0 and V1, are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V0 and V1 pair(s). For each bit in the instruction word, the corresponding bit in V0 and V1 are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.

    摘要翻译： 提出了一种在流水线处理器内选择要监视的指令的方法和装置。 存储在控制寄存器中的一对或多对匹配值被分配用于指令采样或指令匹配。 这些对，称为V0和V1，一起用于过滤用于采样或指令匹配的指令。 在提取或解码阶段，将指令字逐位比较为V0和V1对。 对于指令字中的每个位，V0和V1中的相应位用于确定是否存在匹配。 如果指令字中的每个位都产生匹配，则该指令有资格进行采样。 如果任何位位置不匹配，则说明不符合条件。 响应于确定该指令有资格进行采样，可以监视该指令的执行。