利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.043 秒)

    Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor
    1.
    发明授权
    Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor 失效
    方法随机或伪随机，无偏差，选择微处理器性能分析指令

    公开(公告)号：US07620801B2

    公开(公告)日：2009-11-17

    申请号：US11055848

    申请日：2005-02-11

    申请人： James Wilson Bishop ,  Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Dung Quoc Nguyen ,  Philip Lee Vitale

    发明人： James Wilson Bishop ,  Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Dung Quoc Nguyen ,  Philip Lee Vitale

    IPC分类号： G06F9/30

    CPC分类号： G06F11/3409 ,  G06F11/3466 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    摘要： A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.

    摘要翻译： 一种用于伪随机，无偏差的方法，用于在微处理器中选择用于标记的指令。 响应于从指令高速缓存读取指令，将与指令相关联的指令标记与线性反馈移位寄存器（LFSR）中的伪随机生成值进行比较。 如果指令标签与LFSR中的值相匹配，则表示指令是标记指令的标记位与指令一起发送到执行单元。 响应于性能监视器的指示，LFSR中的值在选择下一个要标记的指令之前递增。 如果该值等于预定的素数增量，则该值被重置为全部值，以避免与正在执行的码流的任何谐波。 在接收到标记指令之后，执行单元将所标记的位与所选择的事件相结合，并将标记的事件报告给性能监视器。

    Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
    2.
    发明授权
    Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
    线程优先级方法，用于确保同时多线程微处理器的处理公平性

    公开(公告)号：US08418180B2

    公开(公告)日：2013-04-09

    申请号：US12129876

    申请日：2008-05-30

    申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

    发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

    IPC分类号： G06F9/46

    CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

    摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

    摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

    Processor including age tracking of issue queue instructions
    5.
    发明授权
    Processor including age tracking of issue queue instructions 有权
    处理器包括发布队列指令的年龄跟踪

    公开(公告)号：US08380964B2

    公开(公告)日：2013-02-19

    申请号：US12417878

    申请日：2009-04-03

    申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

    发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

    IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

    CPC分类号： G06F9/3855

    摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.

    摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

    PROCESSOR INCLUDING AGE TRACKING OF ISSUE QUEUE INSTRUCTIONS
    7.
    发明申请
    PROCESSOR INCLUDING AGE TRACKING OF ISSUE QUEUE INSTRUCTIONS 有权
    处理器包括年龄跟踪问题的指令

    公开(公告)号：US20110185159A1

    公开(公告)日：2011-07-28

    申请号：US12417878

    申请日：2009-04-03

    申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

    发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3855

    摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.

    摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

    Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
    9.
    发明授权
    Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
    线程优先级方法，用于确保同时多线程微处理器的处理公平性

    公开(公告)号：US07631308B2

    公开(公告)日：2009-12-08

    申请号：US11055850

    申请日：2005-02-11

    申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

    发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

    IPC分类号： G06F9/46

    CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

    摘要： A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

    摘要翻译： 在数据处理系统中公开了一种用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性的方法。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。

    Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors
    10.
    发明申请
    Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors 失效
    用于确保同时多线程微处理器处理公平性的线程优先级方法

    公开(公告)号：US20080294884A1

    公开(公告)日：2008-11-27

    申请号：US12129876

    申请日：2008-05-30

    申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

    发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

    摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

    摘要翻译： 在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。