公开(公告)号：US06583747B1

公开(公告)日：2003-06-24

申请号：US10158773

申请日：2002-05-31

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

IPC: H03M112

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

公开(公告)号：US07324038B2

公开(公告)日：2008-01-29

申请号：US10625702

申请日：2003-07-24

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Ruby van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Ruby van de Plassche ,  Marcel Lugthart

IPC: H03M1/12

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US07710184B2

公开(公告)日：2010-05-04

申请号：US11523694

申请日：2006-09-20

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

IPC: H03K5/00

CPC classification number: H03H19/004

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract translation: 本发明涉及信号处理电路，更具体地说，涉及开关电容器电路以及减少符号间干扰的方法。 提供了具有减小的符号间干扰效应的开关电容器电路，包括：电压源，第一电容器，第二电容器和至少一个开关，其被配置为以将第一电容器充电到第一电容器 电压，然后通过第二电容器放电，从而减少符号间干扰效应。

公开(公告)号：US20070182476A1

公开(公告)日：2007-08-09

申请号：US11523694

申请日：2006-09-20

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward

IPC: G06G7/18

CPC classification number: H03H19/004

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract translation: 本发明涉及信号处理电路，更具体地说，涉及开关电容器电路以及减少符号间干扰的方法。 提供了具有减小的符号间干扰效应的开关电容器电路，包括：电压源，第一电容器，第二电容器和至少一个开关，其被配置为以将第一电容器充电到第一电容器 电压，然后通过第二电容器放电，从而减少符号间干扰效应。

公开(公告)号：US06664910B1

公开(公告)日：2003-12-16

申请号：US10460622

申请日：2003-06-13

Applicant: Jan Mulder ,  Christopher Michael Ward

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M112

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

公开(公告)号：US06653966B1

公开(公告)日：2003-11-25

申请号：US10359201

申请日：2003-02-06

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

IPC: H03M100

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US06831585B2

公开(公告)日：2004-12-14

申请号：US10684444

申请日：2003-10-15

Applicant: Jan Mulder ,  Christopher Michael Ward

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M112

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract translation: 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。

公开(公告)号：US06628224B1

公开(公告)日：2003-09-30

申请号：US10153709

申请日：2002-05-24

Applicant: Jan Mulder ,  Christopher Michael Ward

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M112

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract translation: 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。

公开(公告)号：US07800449B2

公开(公告)日：2010-09-21

申请号：US11060395

申请日：2005-02-17

Applicant: Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

IPC: H03F3/04

CPC classification number: H03H11/32

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract translation: 提供了在提供共模电压控制的同时执行单端到差分转换的电路。 电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。 稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。 比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。 调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。

公开(公告)号：US20100186666A1

公开(公告)日：2010-07-29

申请号：US12664648

申请日：2008-06-13

Applicant: Johannes Kappeler ,  Adam Boyd ,  Victor Saywell ,  Jan Mulder ,  Olivier Feron

Inventor： Johannes Kappeler ,  Adam Boyd ,  Victor Saywell ,  Jan Mulder ,  Olivier Feron

IPC: B05C11/00

CPC classification number: C23C16/4586 ,  C23C16/4583 ,  C23C16/46 ,  C30B25/12 ,  H01L21/68735

Abstract: The invention relates to a device for coating substrates having a process chamber (1) disposed in a reactor housing and a two-part, substantially cup-shaped susceptor (2, 3) disposed therein, forming an upper susceptor part (3) with the cup floor thereof having a flat plate (2) and a lower susceptor part (3) with the cup side walls thereof, the outer side (4) of the plate (2) of the upper susceptor part (2) facing upwards toward the process chamber (1) and forming a contact surface for at least one substrate, the upper susceptor part (2) contacting a front edge (3′) of the lower susceptor part (3) at the edge of said upper susceptor part (2), the lower susceptor part (3) being supported by a susceptor carrier (6), and heating zones (A, B, C) for heating the upper susceptor part (2) being disposed below the plate (2′). An advantageous refinement of the invention proposes that the upper susceptor part (2) be removable from the process chamber (1) separately from the lower susceptor part (3), and the joint between the edge of the upper susceptor part (2) and the front edge (3′) of the lower susceptor part (3) be formed as a heat conduction barrier.

Abstract translation: 本发明涉及一种用于涂覆基材的装置，其具有设置在反应器壳体中的处理室（1）和设置在反应器壳体中的两部分基本杯形基座（2,3），形成上基座部分（3），其中 其底板具有平板（2）和具有杯侧壁的下基座部分（3），上托架部分（2）的板（2）的外侧（4）朝向处理 并且形成用于至少一个基板的接触表面，所述上基座部分（2）在所述上基座部分（2）的边缘处接触下基座部分（3）的前边缘（3'）， 下基座部分（3）由基座托架（6）支撑，加热区（A，B，C）用于加热设置在板（2'）下方的上基座部分（2）。 本发明的有益改进提出，上基座部分（2）可以与下基座部分（3）分离地从处理室（1）移除，并且上基座部分（2）的边缘与 下感受器部分（3）的前边缘（3'）形成为导热屏障。