公开(公告)号：US20070136529A1

公开(公告)日：2007-06-14

申请号：US11564695

申请日：2006-11-29

申请人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

发明人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G06K19/07381 ,  G06F11/1441 ,  G06F21/55

摘要： A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

摘要翻译： 用于非易失性存储状态值的装置，其指示已经存在包括非易失性存储器的状况的值，用于在施加电源电压时存储能量的能量存储器以及用于将能量存储器耦合到非易失性存储器的开关电路 - 如果条件存在，则将其状态值写入其中。

公开(公告)号：US07660169B2

公开(公告)日：2010-02-09

申请号：US11564695

申请日：2006-11-29

申请人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

发明人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

IPC分类号： G11C7/00

CPC分类号： G06K19/07381 ,  G06F11/1441 ,  G06F21/55

摘要： A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

摘要翻译： 用于非易失性存储状态值的装置，其指示已经存在包括非易失性存储器的状况的值，用于在施加电源电压时存储能量的能量存储器以及用于将能量存储器耦合到非易失性存储器的开关电路 - 如果条件存在，则将其状态值写入其中。

公开(公告)号：US07552273B2

公开(公告)日：2009-06-23

申请号：US11555799

申请日：2006-11-02

申请人： Jan Otterstedt ,  Holger Sedlak

发明人： Jan Otterstedt ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G11C16/3418 ,  G11C16/3431

摘要： A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

摘要翻译： 一种具有多个存储区域的存储器电路，其顺序依赖于分别相关的逻辑地址，并且每个存储区域具有相关联的控制值，以及控制装置，其被设计为使得其相应于与 当存在时，对应于最低使用存储区域的值的目标存储区域，当存在时，分配相同的任意或预定值，当不存在时，以及当满足预定条件时，以及当处于 存在至少两个使用的存储区域，重写其控制值与最低存储区域的控制值具有预定关系的下一个存储区域的内容，并且改变该存储区域的控制值，当存在​​该存储区域的存储区域存在时，或者重写 最低存储器区域的内容并且改变相关联的控制值，当下一个存储区域的控制值与最低存储器ar的控制值具有预定的关系时 ea，不存在。

公开(公告)号：US20080126717A1

公开(公告)日：2008-05-29

申请号：US11555799

申请日：2006-11-02

申请人： Jan Otterstedt ,  Holger Sedlak

发明人： Jan Otterstedt ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G11C16/3418 ,  G11C16/3431

摘要： A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

摘要翻译： 一种具有多个存储区域的存储器电路，其顺序依赖于分别相关的逻辑地址，并且每个存储区域具有相关联的控制值，以及控制装置，其被设计为使得其相应于与 当存在时，对应于最低使用存储区域的值的目标存储区域，当存在时，分配相同的任意或预定值，当不存在时，以及当满足预定条件时，以及当处于 存在至少两个使用的存储区域，重写其控制值与最低存储区域的控制值具有预定关系的下一个存储区域的内容，并且改变该存储区域的控制值，当存在​​该存储区域的存储区域存在时，或者重写 最低存储器区域的内容并且改变相关联的控制值，当下一个存储区域的控制值与最低存储器ar的控制值具有预定的关系时 ea，不存在。

公开(公告)号：US09933190B2

公开(公告)日：2018-04-03

申请号：US12935749

申请日：2009-03-30

申请人： Holger Sedlak ,  Oliver Kniffler

发明人： Holger Sedlak ,  Oliver Kniffler

IPC分类号： F25D17/02 ,  F24D11/02 ,  B21D53/06 ,  F25B1/00 ,  F25B30/06 ,  F24H4/04 ,  F25B1/10 ,  F25B1/053 ,  F25B39/04

CPC分类号： F25B30/06 ,  F24H4/04 ,  F25B1/053 ,  F25B1/10 ,  F25B39/04 ,  F25B2339/047 ,  F25B2400/072 ,  F25B2500/01 ,  Y10T29/49359

摘要： In a heat pump with an evaporator and a liquefier as well as a gas region extending between the evaporator and the liquefier, the liquefier is arranged above the evaporator in a setup direction for operation of the heat pump.

公开(公告)号：US08369520B2

公开(公告)日：2013-02-05

申请号：US12034252

申请日：2008-02-20

申请人： Astrid Elbe ,  Norbert Janssen ,  Holger Sedlak

发明人： Astrid Elbe ,  Norbert Janssen ,  Holger Sedlak

IPC分类号： H04L9/00

CPC分类号： G06F9/3891 ,  G06F7/72 ,  G06F7/723 ,  G06F9/3879 ,  G06F9/3885 ,  G06F21/72 ,  G06F21/755 ,  G06F2207/7266

摘要： A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomized to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

摘要翻译： 密码处理器包括中央处理单元和协处理器，所述协处理器包括多个计算子单元以及耦合到所述多个计算子单元中的每一个的单个控制单元。 通过控制单元以子操作的形式在各​​个计算子单元之间分配加密操作。 中央处理单元，多个计算子单元和控制单元集成在单个芯片上，该芯片包括用于向多个计算子单元和控制单元提供电流的公共供电电流访问。 由于并行计算子单元的配置，手段上增加了密码处理器的吞吐量。 然而，另一方面，可以在供应电流访问中检测到的当前简档被随机化到这样的程度，使得攻击者不再能够推断在各个计算子单元中处理的数字。

公开(公告)号：US20110146316A1

公开(公告)日：2011-06-23

申请号：US12976230

申请日：2010-12-22

申请人： Holger Sedlak ,  Oliver Kniffler

发明人： Holger Sedlak ,  Oliver Kniffler

IPC分类号： F25B27/00 ,  F28F13/12

CPC分类号： F25B30/02 ,  F25B39/00 ,  F25B43/043 ,  F28F13/12 ,  F28F13/182

摘要： An evaporator or a condenser includes a surface on which the operating liquid is arranged. Further, turbulence generators are provided to generate turbulences in the operating liquid located on the operating surface. In the condenser, alternatively or additionally, a laminarizer is present to make the vapor stream laminar provided by the compressor. On the evaporator side, the evaporation efficiency is increased and, on the condenser side, the condenser efficiency is increased, which may be used for a substantial reduction in size without loss of power of these components, in particular for a heat pump for heating a building.

摘要翻译： 蒸发器或冷凝器包括其上布置有操作液体的表面。 此外，提供湍流发生器以在位于操作表面上的操作液体中产生湍流。 在冷凝器中，或者或另外，存在层流器以制造由压缩机提供的蒸气流层流。 在蒸发器侧，蒸发效率提高，并且在冷凝器侧，冷凝器的效率增加，其可以用于大大减小尺寸而不损失这些部件的功率，特别是用于加热热泵的热泵 建造。

公开(公告)号：US20110100054A1

公开(公告)日：2011-05-05

申请号：US12935743

申请日：2009-03-30

申请人： Holger Sedlak ,  Oliver Kniffler

发明人： Holger Sedlak ,  Oliver Kniffler

IPC分类号： F25B1/00 ,  B23P15/26

CPC分类号： F25B30/02 ,  F25B31/00 ,  F25B39/04 ,  F25B2400/071 ,  Y10T29/49359

摘要： A liquefier for a heat pump includes a liquefier space, a compressor motor and a motor fixture for holding the stationary motor part, wherein the motor further has a motor shaft and a compressor wheel connected to the motor shaft. The motor fixture is formed so that the stationary motor part is held so that it is in contact with liquefied working fluid when liquefied working fluid is filled in the liquefier space. Furthermore, the compressor wheel extends into a region of the heat pump in which a channel for gaseous working fluid to be compressed passes.

摘要翻译： 用于热泵的液化器包括液化空间，压缩机电动机和用于保持固定电动机部件的电动机固定装置，其中电动机还具有连接到电动机轴的电动机轴和压缩机叶轮。 电动机固定装置形成为使得固定电动机部分被保持成使得当液化工作流体填充在液化空间中时与液化工作流体接触。 此外，压缩机叶轮延伸到热泵的区域，在该区域中待压缩的气态工作流体的通道通过。

公开(公告)号：US07698357B2

公开(公告)日：2010-04-13

申请号：US11165834

申请日：2005-06-23

申请人： Wieland Fischer ,  Holger Sedlak ,  Jean-Pierre Seifert

发明人： Wieland Fischer ,  Holger Sedlak ,  Jean-Pierre Seifert

IPC分类号： G06F15/00

CPC分类号： G06F7/722

摘要： A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.

摘要翻译： 用于计算乘法器和乘法器的乘法的装置包括执行精确三个操作数相加的第一执行器和执行近似操作数相加的第二执行器，以及使用近似中间结果来计算当前先行参数的计算器。 第一执行者进一步实施，以在当前迭代步骤中使用当前迭代步骤的确切中间结果并使用为当前迭代步骤计算的预先参数来执行精确的三操作数添加。

公开(公告)号：US07599383B2

公开(公告)日：2009-10-06

申请号：US10662794

申请日：2003-09-15

申请人： Oliver Kniffler ,  Holger Sedlak

发明人： Oliver Kniffler ,  Holger Sedlak

IPC分类号： H04J3/16 ,  H04L12/40 ,  H04B7/212

CPC分类号： G06F13/4217

摘要： A data bus configuration has a data bus which can be operated in a multiplex mode and to which at least one control station and a reception station are connected. The data bus configuration further has a control bus via which the control station can allocate a logical channel to the reception station.

摘要翻译： 数据总线配置具有数据总线，其可以以多路复用方式操作，至少一个控制站和接收站连接到该数据总线。 数据总线配置还具有控制总线，控制站可以经由该控制总线向接收站分配逻辑信道。