公开(公告)号：US20070136529A1

公开(公告)日：2007-06-14

申请号：US11564695

申请日：2006-11-29

申请人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

发明人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G06K19/07381 ,  G06F11/1441 ,  G06F21/55

摘要： A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

摘要翻译： 用于非易失性存储状态值的装置，其指示已经存在包括非易失性存储器的状况的值，用于在施加电源电压时存储能量的能量存储器以及用于将能量存储器耦合到非易失性存储器的开关电路 - 如果条件存在，则将其状态值写入其中。

公开(公告)号：US07660169B2

公开(公告)日：2010-02-09

申请号：US11564695

申请日：2006-11-29

申请人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

发明人： Jan Otterstedt ,  Christian Peters ,  Dirk Rabe ,  Holger Sedlak

IPC分类号： G11C7/00

CPC分类号： G06K19/07381 ,  G06F11/1441 ,  G06F21/55

摘要： A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

摘要翻译： 用于非易失性存储状态值的装置，其指示已经存在包括非易失性存储器的状况的值，用于在施加电源电压时存储能量的能量存储器以及用于将能量存储器耦合到非易失性存储器的开关电路 - 如果条件存在，则将其状态值写入其中。

公开(公告)号：US07552273B2

公开(公告)日：2009-06-23

申请号：US11555799

申请日：2006-11-02

申请人： Jan Otterstedt ,  Holger Sedlak

发明人： Jan Otterstedt ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G11C16/3418 ,  G11C16/3431

摘要： A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

摘要翻译： 一种具有多个存储区域的存储器电路，其顺序依赖于分别相关的逻辑地址，并且每个存储区域具有相关联的控制值，以及控制装置，其被设计为使得其相应于与 当存在时，对应于最低使用存储区域的值的目标存储区域，当存在时，分配相同的任意或预定值，当不存在时，以及当满足预定条件时，以及当处于 存在至少两个使用的存储区域，重写其控制值与最低存储区域的控制值具有预定关系的下一个存储区域的内容，并且改变该存储区域的控制值，当存在​​该存储区域的存储区域存在时，或者重写 最低存储器区域的内容并且改变相关联的控制值，当下一个存储区域的控制值与最低存储器ar的控制值具有预定的关系时 ea，不存在。

公开(公告)号：US20080126717A1

公开(公告)日：2008-05-29

申请号：US11555799

申请日：2006-11-02

申请人： Jan Otterstedt ,  Holger Sedlak

发明人： Jan Otterstedt ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G11C16/3418 ,  G11C16/3431

摘要： A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

摘要翻译： 一种具有多个存储区域的存储器电路，其顺序依赖于分别相关的逻辑地址，并且每个存储区域具有相关联的控制值，以及控制装置，其被设计为使得其相应于与 当存在时，对应于最低使用存储区域的值的目标存储区域，当存在时，分配相同的任意或预定值，当不存在时，以及当满足预定条件时，以及当处于 存在至少两个使用的存储区域，重写其控制值与最低存储区域的控制值具有预定关系的下一个存储区域的内容，并且改变该存储区域的控制值，当存在​​该存储区域的存储区域存在时，或者重写 最低存储器区域的内容并且改变相关联的控制值，当下一个存储区域的控制值与最低存储器ar的控制值具有预定的关系时 ea，不存在。

公开(公告)号：US07415602B2

公开(公告)日：2008-08-19

申请号：US11017209

申请日：2004-12-20

申请人： Dirk Rabe ,  Holger Sedlak

发明人： Dirk Rabe ,  Holger Sedlak

IPC分类号： G06F9/42 ,  G06F9/44 ,  G06F12/10

CPC分类号： G06F9/30054 ,  G06F9/4486

摘要： An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or FCALL, a stack memory is filled, while the stack is emptied in the case of the presence of a re-jump instruction. At every re-jump, a predetermined amount of re-jump information is taken from stack and supplied to a means for decoding, which is formed to access the stack again in the case where the predetermined amount of re-jump information indicates a change of the physical memory window, to finally supply the correct address for the next instruction in the instruction sequence to the means for reading in. Thereby, the same re-jump instruction can be used for a call with FCALL (outside of a current physical memory window) and a call with LCALL (within the physical memory window), without a microprocessor change, by encoding the re-jump information on the stack and by decoding them by the means for decoding. Thereby, the re-jump instruction provided for the microprocessor can be used for both jump instructions.

摘要翻译： 一种用于处理包括LCALL指令，FCALL指令和公共重新跳转指令（返回））指令序列的装置，包括用于读取指令的装置，以执行用于 检查说明。 在存在LCALL或FCALL的情况下，填充堆栈内存，而在存在重新跳转指令的情况下堆栈被清空。 在每次重新跳跃时，从堆栈取出预定量的重跳信息，并提供给解码装置，该装置形成为在预定量的重跳信息指示改变的情况下再次访问堆栈 物理存储器窗口，最终为指令序列中的下一个指令提供正确的地址以供读取装置。因此，可以使用与FCALL（当前物理存储器窗口外部）的调用相同的重新跳转指令 ）和具有LCALL（在物理存储器窗口内）的呼叫，而不需要微处理器改变，通过对堆栈上的重新跳转信息进行编码，并通过解码装置进行解码。 因此，为微处理器提供的重新跳转指令可以用于两个跳转指令。

公开(公告)号：US20050154868A1

公开(公告)日：2005-07-14

申请号：US11017209

申请日：2004-12-20

申请人： Dirk Rabe ,  Holger Sedlak

发明人： Dirk Rabe ,  Holger Sedlak

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/42 ,  G06F9/44 ,  G06F9/45

CPC分类号： G06F9/30054 ,  G06F9/4486

摘要： An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or FCALL, a stack memory is filled, while the stack is emptied in the case of the presence of a re-jump instruction. At every re-jump, a predetermined amount of re-jump information is taken from stack and supplied to a means for decoding, which is formed to access the stack again in the case where the predetermined amount of re-jump information indicates a change of the physical memory window, to finally supply the correct address for the next instruction in the instruction sequence to the means for reading in. Thereby, the same re-jump instruction can be used for a call with FCALL (outside of a current physical memory window) and a call with LCALL (within the physical memory window), without a microprocessor change, by encoding the re-jump information on the stack and by decoding them by the means for decoding. Thereby, the re-jump instruction provided for the microprocessor can be used for both jump instructions.

摘要翻译： 一种用于处理包括LCALL指令，FCALL指令和公共重新跳转指令（返回））指令序列的装置，包括用于读取指令的装置，以执行用于 检查说明。 在存在LCALL或FCALL的情况下，填充堆栈内存，而在存在重新跳转指令的情况下堆栈被清空。 在每次重新跳跃时，从堆栈取出预定量的重跳信息，并提供给解码装置，该装置形成为在预定量的重跳信息指示改变的情况下再次访问堆栈 物理存储器窗口，最终为指令序列中的下一个指令提供正确的地址以供读取装置。因此，可以使用与FCALL（当前物理存储器窗口外部）的调用相同的重新跳转指令 ）和具有LCALL（在物理存储器窗口内）的呼叫，而不需要微处理器改变，通过对堆栈上的重新跳转信息进行编码，并通过解码装置进行解码。 因此，为微处理器提供的重新跳转指令可以用于两个跳转指令。

公开(公告)号：US06940755B2

公开(公告)日：2005-09-06

申请号：US10768988

申请日：2004-01-30

申请人： Christian Peters ,  Holger Sedlak

发明人： Christian Peters ,  Holger Sedlak

IPC分类号： G11C16/06 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C16/26

摘要： A selection transistor for a group of memory cells, preferably composed of 16-32 memory cells, is respectively introduced into the feed lines to the memory cells The selection transistor is opened to a line group for reading, while the control gates of all lines are low potential, and the current for each reading column leading through said line group is measured and stored. In a second step, the control gate of the line to be read is brought to a higher reading potential and the resulting current is compared to the previous current.

摘要翻译： 用于一组存储器单元的选择晶体管，优选地由16-32个存储单元组成，分别被引入到存储单元的馈线中。选择晶体管被打开到用于读取的线组，而所有线的控制栅极是 测量并存储通过所述线组导通的每个读取列的电流。 在第二步中，要读取的线路的控制栅极变为更高的读取电位，并将所得到的电流与先前的电流进行比较。

公开(公告)号：US20050251643A1

公开(公告)日：2005-11-10

申请号：US11125819

申请日：2005-05-09

申请人： Gerd Dirscherl ,  Christian Peters ,  Holger Sedlak

发明人： Gerd Dirscherl ,  Christian Peters ,  Holger Sedlak

IPC分类号： G11C16/10 ,  G06F12/08

CPC分类号： G11C16/105 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/102

摘要： A memory arrangement and method for operating the memory arrangement comprising a nonvolatile memory and at least one address translation unit, the nonvolatile memory having memory pages and at least one additional memory page, the memory pages and the additional memory page having physical addresses and the address translation unit translating logically addressable addresses into the physical addresses of the memory pages and of the additional memory page. The nonvolatile memory stores data which make address translation possible within an unaddressable area in the memory pages and in the additional memory page. For the purposes of programming a memory page, a copy of data and a copy of the data of the unaddressable area are stored in a further memory for processing and the data of the unaddressable area are changed. Once programming has been completed, the processed copy of the data and the changed data of the unaddressable area are stored in the additional memory page.

摘要翻译： 一种用于操作存储器装置的存储器装置和方法，包括非易失性存储器和至少一个地址转换单元，所述非易失性存储器具有存储器页面和至少一个附加存储器页面，存储器页面和附加存储器页面具有物理地址和地址 翻译单元将逻辑可寻址地址转换为存储器页面和附加存储器页面的物理地址。 非易失性存储器存储使存储器页面和附加存储器页面中的不可寻址区域内的地址转换成为可能的数据。 为了编程存储器页面，将数据副本和不可寻址区域的数据的副本存储在另外的存储器中用于处理，并且改变不可寻址区域的数据。 一旦编程完成，数据的处理副本和不可寻址区域的更改数据就被存储在附加存储器页面中。

公开(公告)号：US09933190B2

公开(公告)日：2018-04-03

申请号：US12935749

申请日：2009-03-30

申请人： Holger Sedlak ,  Oliver Kniffler

发明人： Holger Sedlak ,  Oliver Kniffler

IPC分类号： F25D17/02 ,  F24D11/02 ,  B21D53/06 ,  F25B1/00 ,  F25B30/06 ,  F24H4/04 ,  F25B1/10 ,  F25B1/053 ,  F25B39/04

CPC分类号： F25B30/06 ,  F24H4/04 ,  F25B1/053 ,  F25B1/10 ,  F25B39/04 ,  F25B2339/047 ,  F25B2400/072 ,  F25B2500/01 ,  Y10T29/49359

摘要： In a heat pump with an evaporator and a liquefier as well as a gas region extending between the evaporator and the liquefier, the liquefier is arranged above the evaporator in a setup direction for operation of the heat pump.

公开(公告)号：US08369520B2

公开(公告)日：2013-02-05

申请号：US12034252

申请日：2008-02-20

申请人： Astrid Elbe ,  Norbert Janssen ,  Holger Sedlak

发明人： Astrid Elbe ,  Norbert Janssen ,  Holger Sedlak

IPC分类号： H04L9/00

CPC分类号： G06F9/3891 ,  G06F7/72 ,  G06F7/723 ,  G06F9/3879 ,  G06F9/3885 ,  G06F21/72 ,  G06F21/755 ,  G06F2207/7266

摘要： A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomized to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

摘要翻译： 密码处理器包括中央处理单元和协处理器，所述协处理器包括多个计算子单元以及耦合到所述多个计算子单元中的每一个的单个控制单元。 通过控制单元以子操作的形式在各​​个计算子单元之间分配加密操作。 中央处理单元，多个计算子单元和控制单元集成在单个芯片上，该芯片包括用于向多个计算子单元和控制单元提供电流的公共供电电流访问。 由于并行计算子单元的配置，手段上增加了密码处理器的吞吐量。 然而，另一方面，可以在供应电流访问中检测到的当前简档被随机化到这样的程度，使得攻击者不再能够推断在各个计算子单元中处理的数字。