公开(公告)号：US08395244B2

公开(公告)日：2013-03-12

申请号：US12942410

申请日：2010-11-09

Applicant: Jan Vobecky ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

Inventor： Jan Vobecky ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

IPC: H01L21/02

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm−3 and 2*1017 cm−3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 μm. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm−3 and 1*1015 cm−3 is reached between a first depth, which is at least 20 μm, and a second depth, which is at maximum 50 μm. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.

Abstract translation: 快速恢复二极管包括具有阴极侧和与阴极侧相对的阳极侧的n掺杂基极层。 p型掺杂阳极层设置在阳极侧。 阳极层具有掺杂分布并且包括至少两个子层。 第一个子层具有第一最大掺杂浓度，其在2×1016cm-3和2×1017cm-3之间，并且高于任何其它子层的最大掺杂浓度。 最后一个子层具有比任何其他子层深度大的最后一个子层深度。 最后的子层深度为90〜120μm。 阳极层的掺杂分布下降，使得在第一深度（至少20μm）和第二深度之间达到在5×10 14 cm -3和1×10 15 cm -3范围内的掺杂浓度，其中 最大为50μm。 通过使用铝扩散层作为至少两个子层来实现掺杂浓度的这种分布。

公开(公告)号：US08501548B2

公开(公告)日：2013-08-06

申请号：US12951334

申请日：2010-11-22

Applicant: Jan Vobecky ,  Munaf Rahimo

Inventor： Jan Vobecky ,  Munaf Rahimo

IPC: H01L21/332

CPC classification number: H01L21/26513 ,  H01L21/268 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.). Boron is an exemplary dopant of the first conductivity type, and phosphorous is an exemplary dopant of the second conductivity type. Boron can be activated in the regions irradiated only with the laser beam, whereas phosphorus may be activated in a low temperature sintering step on the entire surface.

Abstract translation: 一种用于制造具有图案化表面的诸如RC-IGBT或BIGT的半导体器件的方法，其中掺杂有第一导电类型的掺杂剂的部分区域和掺杂有第二导电类型的掺杂剂的区域在半导体衬底的同一侧 被提出。 一种示例性方法包括：（a）将第一导电类型的掺杂剂注入并将第二导电类型的掺杂剂注入到待图案化的表面中; （b）通过使用类似于激光退火中使用的激光束局部加热要构图的表面的部分区域到第一温度（例如在900和1000℃之间）来局部地激活第一导电类型的掺杂剂; 和（c）通过将衬底加热到​​低于第一温度的第二温度（例如，温度低于600℃）来激活第二导电类型的掺杂剂。 硼是第一导电类型的示例性掺杂剂，磷是第二导电类型的示例性掺杂剂。 可以在仅用激光束照射的区域中激活硼，而磷可以在整个表面上的低温烧结步骤中活化。

公开(公告)号：US08415239B2

公开(公告)日：2013-04-09

申请号：US12731977

申请日：2010-03-25

Applicant: Jan Vobecky ,  Munaf Rahimo

Inventor： Jan Vobecky ,  Munaf Rahimo

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L21/221 ,  H01L21/26506 ,  H01L21/266

Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.

Abstract translation: 公开了一种用于制造功率半导体器件的示例性方法，该功率半导体器件在第一主侧具有第一电接触，而在与第一主侧相对的第二主侧上具有第二电接触，以及至少具有不同导电层的两层结构 类型，并且包括提供n掺杂晶片并在第一主侧上产生钯颗粒的表面层。 用离子将晶片照射在第一主面上。 之后，钯粒子在不超过750℃的温度下扩散到晶片中，由此产生第一p掺杂层的扩散。 然后，产生第一和第二电触点。 至少通过掩模进行离子照射。

公开(公告)号：US08450777B2

公开(公告)日：2013-05-28

申请号：US12778751

申请日：2010-05-12

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Arnost Kopta

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Arnost Kopta

IPC: H01L29/66

CPC classification number: H01L29/7395 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66333

Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.

Abstract translation: 反向导通绝缘栅双极晶体管包括具有第二导电类型的第二层和第一导电类型的第三层的第一导电类型的晶片。 第五电绝缘层部分地覆盖这些层。 导电的第四层通过第五层与晶片电绝缘。 第三至第五层在第二层上形成第一开口。 第二导电类型的第六层和第一导电类型的第七层交替地布置在晶片的第二侧上的平面中。 通过使用第四和第五层作为第一掩模通过第一开口注入离子形成第九层。

公开(公告)号：US20100270585A1

公开(公告)日：2010-10-28

申请号：US12778751

申请日：2010-05-12

Applicant: Munaf RAHIMO ,  Jan Vobecky ,  Arnost Kopta

Inventor： Munaf RAHIMO ,  Jan Vobecky ,  Arnost Kopta

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66333

Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.

Abstract translation: 反向导通绝缘栅双极晶体管包括具有第二导电类型的第二层和第一导电类型的第三层的第一导电类型的晶片。 第五电绝缘层部分地覆盖这些层。 导电的第四层通过第五层与晶片电绝缘。 第三至第五层在第二层上形成第一开口。 第二导电类型的第六层和第一导电类型的第七层交替地布置在晶片的第二侧上的平面中。 通过使用第四和第五层作为第一掩模通过第一开口注入离子形成第九层。

公开(公告)号：US08829571B2

公开(公告)日：2014-09-09

申请号：US13468593

申请日：2012-05-10

Applicant: Munaf Rahimo ,  Arnost Kopta ,  Jan Vobecky ,  Wolfgang Janisch

Inventor： Munaf Rahimo ,  Arnost Kopta ,  Jan Vobecky ,  Wolfgang Janisch

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0611 ,  H01L29/66333

Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ⁢ ⁢ kV ⁢ ⁢ cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.

Abstract translation: 公开了诸如绝缘栅双极晶体管（IGBT）或二极管的最大穿通半导体器件及其制造方法。 MPT半导体器件可以包括具有发射极金属化的至少两层结构，沟道区，具有预定掺杂浓度ND的基极层，缓冲层和集电极金属化。 基底层的厚度W可以通过以下公式确定：W = V bd + V pt 4010注册kV电容cm -5 / 8 *（ND）1/8其中半导体器件的穿通电压Vpt在 70％和99％的半导体器件的击穿电压Vbd，并且其中厚度W是在结到通道区域与缓冲层之间的基底层的最小厚度。

公开(公告)号：US08450793B2

公开(公告)日：2013-05-28

申请号：US12753570

申请日：2010-04-02

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

IPC: H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer.

Abstract translation: 公开了具有四层结构的受控穿通半导体器件，其包括不同导电类型的层，集电极侧的集电极和位于集电极侧的发射极侧的发射极。 半导体器件可以通过以下顺序执行的方法制造：在第一导电类型的晶片的发射极侧产生层; 在第二面上稀薄晶片; 将第一导电类型的颗粒施加到集电极侧的晶片，以形成第一深度的第一峰值掺杂浓度高于晶片掺杂的第一缓冲层; 将第二导电类型的颗粒施加到第二侧上的晶片，以在集电极侧上形成集电极层; 以及在第二面上形成收集器金属化。 在任何阶段，可以将第一导电类型的颗粒施加到第二侧上的晶片，以形成具有低于第一缓冲层的第一峰掺杂浓度的第二峰值掺杂浓度的第二缓冲层，但高于掺杂 晶圆。 可以在第一深度和第二深度之间布置第三缓冲层，其掺杂浓度低于第二缓冲层的第二峰值掺杂浓度。 热处理可以用于形成第一缓冲层，第二缓冲层和/或集电体层。

公开(公告)号：US20100244093A1

公开(公告)日：2010-09-30

申请号：US12753570

申请日：2010-04-02

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer.

Abstract translation: 公开了具有四层结构的受控穿通半导体器件，其包括不同导电类型的层，集电极侧的集电极和位于集电极侧的发射极侧的发射极。 半导体器件可以通过以下顺序执行的方法制造：在第一导电类型的晶片的发射极侧产生层; 在第二面上稀薄晶片; 将第一导电类型的颗粒施加到集电极侧的晶片，以形成第一深度的第一峰值掺杂浓度高于晶片掺杂的第一缓冲层; 将第二导电类型的颗粒施加到第二侧上的晶片，以在集电极侧上形成集电极层; 以及在第二面上形成收集器金属化。 在任何阶段，可以将第一导电类型的颗粒施加到第二侧上的晶片，以形成具有低于第一缓冲层的第一峰掺杂浓度的第二峰值掺杂浓度的第二缓冲层，但高于掺杂 晶圆。 可以在第一深度和第二深度之间布置第三缓冲层，其掺杂浓度低于第二缓冲层的第二峰值掺杂浓度。 热处理可以用于形成第一缓冲层，第二缓冲层和/或集电体层。

公开(公告)号：US08912623B2

公开(公告)日：2014-12-16

申请号：US12942476

申请日：2010-11-09

Applicant: Jan Vobecky ,  Arnost Kopta ,  Marta Cammarata

Inventor： Jan Vobecky ,  Arnost Kopta ,  Marta Cammarata

IPC: H01L29/739 ,  H01L29/32 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L29/32 ,  H01L29/66136

Abstract: A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths.

Abstract translation: 快速恢复二极管包括第一导电类型的基极层。 基底层具有与阴极侧相反的阴极侧和阳极侧。 具有第一深度和第一最大掺杂浓度的第二导电类型的阳极缓冲层布置在阳极侧。 具有比第一深度低的第二深度的第二导电类型的阳极接触层和高于第一最大掺杂浓度的第二最大掺杂浓度也布置在阳极侧。 在击穿电压下的阳极结的空间电荷区域位于第一和第二深度之间的第三深度。 在第二和第三深度之间布置具有缺陷峰的缺陷层。

公开(公告)号：US20110108941A1

公开(公告)日：2011-05-12

申请号：US12942476

申请日：2010-11-09

Applicant: Jan Vobecky ,  Arnost Kopta ,  Marta Cammarata

Inventor： Jan Vobecky ,  Arnost Kopta ,  Marta Cammarata

IPC: H01L29/872 ,  H01L29/87 ,  H01L29/739 ,  H01L21/266

CPC classification number: H01L29/861 ,  H01L29/32 ,  H01L29/66136

Abstract: A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths.

Abstract translation: 快速恢复二极管包括第一导电类型的基极层。 基底层具有与阴极侧相反的阴极侧和阳极侧。 具有第一深度和第一最大掺杂浓度的第二导电类型的阳极缓冲层布置在阳极侧。 具有比第一深度低的第二深度的第二导电类型的阳极接触层和高于第一最大掺杂浓度的第二最大掺杂浓度也布置在阳极侧。 在击穿电压下的阳极结的空间电荷区域位于第一和第二深度之间的第三深度。 在第二和第三深度之间布置具有缺陷峰的缺陷层。