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    METHOD OF MANUFACTURING THIN-FILM TRANSISTOR
    1.
    发明申请
    METHOD OF MANUFACTURING THIN-FILM TRANSISTOR 有权
    制造薄膜晶体管的方法

    公开(公告)号：US20160211177A1

    公开(公告)日：2016-07-21

    申请号：US14996323

    申请日：2016-01-15

    Applicant: Japan Display Inc.

    Inventor： lsao SUZUMURA ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  Yohei YAMAGUCHI

    IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

    CPC classification number: H01L21/76895 ,  H01L21/022 ,  H01L21/32136 ,  H01L21/465 ,  H01L21/78 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

    Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.

    Abstract translation: 根据一个实施例，制造薄膜晶体管的方法包括在绝缘层12插入的栅电极上形成半导体层，在半导体层上形成互连形成层，通过图案化形成多个互连和电极 通过蚀刻进行互连形成层，在形成电极之后通过蚀刻将半导体层图案化为岛状，通过蚀刻半导体层上的一部分电极来暴露半导体层的沟道区域，并形成保护层以重叠 互连，电极和具有岛状的半导体层。

    DISPLAY DEVICE
    3.
    发明申请
    DISPLAY DEVICE 有权

    公开(公告)号：US20230020074A1

    公开(公告)日：2023-01-19

    申请号：US17945214

    申请日：2022-09-15

    Applicant: Japan Display Inc.

    Inventor： Yohei YAMAGUCHI ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  Isao SUZUMURA

    IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343

    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

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