公开(公告)号：US20230020074A1

公开(公告)日：2023-01-19

申请号：US17945214

申请日：2022-09-15

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  Isao SUZUMURA

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

公开(公告)号：US20180040645A1

公开(公告)日：2018-02-08

申请号：US15661086

申请日：2017-07-27

Applicant: Japan Display Inc.

Inventor： Yoshinori ISHII ,  Kazufumi WATABE ,  Hidekazu MIYAKE

IPC: H01L27/12

Abstract: An organic EL display device has a semiconductor circuit substrate comprising a TFT and an organic passivation layer thereon. An AlO layer is formed over the organic passivation layer, and an electrode layer is formed on the AlO layer. The electrode layer connects with TFT via a through hole formed in the AlO layer and in the organic passivation layer.

公开(公告)号：US20160163741A1

公开(公告)日：2016-06-09

申请号：US15015445

申请日：2016-02-04

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Norihiro UEMURA ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L21/02071 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/473 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.

公开(公告)号：US20160043232A1

公开(公告)日：2016-02-11

申请号：US14920647

申请日：2015-10-22

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Isao SUZUMURA

IPC: H01L29/786 ,  G02F1/1335 ,  G02F1/1368 ,  H01L27/12

CPC classification number: H01L29/78606 ,  G02F1/133602 ,  G02F1/1368 ,  H01L27/1225 ,  H01L29/7869

Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.

公开(公告)号：US20150179812A1

公开(公告)日：2015-06-25

申请号：US14573124

申请日：2014-12-17

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Norihiro UEMURA ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L29/786 ,  H01L21/473 ,  H01L21/4763 ,  H01L21/033 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L21/02071 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/473 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.

Abstract translation: 提供了可以抑制初始Vth耗尽和Vth偏移的底栅通道蚀刻薄膜晶体管。 形成薄膜晶体管，其包括设置在基板上的栅电极互连，栅极绝缘膜，作为沟道层的氧化物半导体层，源极互连的叠层膜和第一硬掩模层，层叠膜 的漏电极互连和第二硬掩模层，以及保护绝缘膜。

公开(公告)号：US20140362059A1

公开(公告)日：2014-12-11

申请号：US14300257

申请日：2014-06-10

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  Hidekazu MIYAKE ,  Takeshi NODA ,  Isao SUZUMURA ,  Yohei YAMAGUCHI

IPC: H01L27/12 ,  G09G5/00 ,  H01L29/786

CPC classification number: G09G5/00 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

Abstract: A thin film transistor includes a drain electrode layer and a source electrode layer that are formed above an oxide semiconductor layer via an insulating film. The drain electrode layer and the source electrode layer are electrically connected with the oxide semiconductor layer via through-holes formed in the insulating film. A first through-hole that electrically connects the drain electrode layer with the oxide semiconductor layer and a second through-hole that electrically connects the source electrode layer with the oxide semiconductor layer each include two or more through-holes that are arranged in parallel in a channel width direction of the thin film transistor. A total width of opening widths of the first or second through-holes in the channel width direction is a channel width of the thin film transistor.

Abstract translation: 薄膜晶体管包括通过绝缘膜形成在氧化物半导体层上方的漏电极层和源极电极层。 漏电极层和源电极层通过形成在绝缘膜中的通孔与氧化物半导体层电连接。 将漏电极层与氧化物半导体层电连接的第一通孔和将源电极层与氧化物半导体层电连接的第二通孔各自包括两个或更多个平行布置的通孔， 薄膜晶体管的沟道宽度方向。 沟道宽度方向上的第一或第二通孔的开口宽度的总宽度是薄膜晶体管的沟道宽度。

公开(公告)号：US20240184177A1

公开(公告)日：2024-06-06

申请号：US18428228

申请日：2024-01-31

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  Isao SUZUMURA

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869 ,  G02F1/136218 ,  G02F1/13685 ,  G02F2202/10 ,  H01L29/42384

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

公开(公告)号：US20240130165A1

公开(公告)日：2024-04-18

申请号：US18483529

申请日：2023-10-10

Applicant: Japan Display Inc.

Inventor： Hidekazu MIYAKE ,  Naoki TOKUDA

IPC: H10K59/122 ,  H10K59/12 ,  H10K59/80

CPC classification number: H10K59/122 ,  H10K59/1201 ,  H10K59/873 ,  H10K59/352

Abstract: According to one embodiment, a display device includes a plurality of display elements and a partition which surrounds each of the plurality of display elements. The display elements each include a lower electrode, an upper electrode opposing the lower electrode and an organic layer disposed between the lower electrode and the upper electrode. The partition includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion. Further, the partition includes an aperture through which the lower portion and the upper portion penetrate.

公开(公告)号：US20180040644A1

公开(公告)日：2018-02-08

申请号：US15659796

申请日：2017-07-26

Applicant: Japan Display Inc.

Inventor： Yoshinori ISHII ,  Kazufumi WATABE ,  Hidekazu MIYAKE

IPC: H01L27/12 ,  G02F1/1362 ,  H01L51/56 ,  H01L27/32 ,  H01L51/52 ,  G02F1/1368 ,  G02F1/1333

CPC classification number: H01L27/1248 ,  G02F1/1303 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/501 ,  G02F2202/022 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L51/5218 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/556 ,  H01L2251/558

Abstract: Separation of wirings formed on an organic passivation film is prevented in an organic EL display device or a liquid crystal display device. The organic EL display device includes a TFT formed on a substrate and an organic passivation film formed to cover the TFT. An intermediate film containing SiO or SiN is formed to cover the organic passivation film. An insulation film formed with an organic material is formed on the intermediate film. A reflective electrode is formed on the intermediate film. The reflective electrode is connected to the TFT via a through-hole formed in the organic passivation film and a through-hole formed in the intermediate film.

公开(公告)号：US20170343845A1

公开(公告)日：2017-11-30

申请号：US15662385

申请日：2017-07-28

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  Isao SUZUMURA

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/13685 ,  G02F2202/10 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78633 ,  H01L29/7869

Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.