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1.发明授权Address-based hazard resolution for managing read/write operations in a memory cache 失效用于管理内存缓存中的读/写操作的基于地址的危险解决方案公开(公告)号：US08639889B2
公开(公告)日：2014-01-28
申请号：US13017250
申请日：2011-01-31
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0857 , Y02D10/13
摘要： One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.
摘要翻译： 一个实施例提供了一种缓存的存储器系统，其包括存储器高速缓存和被配置用于执行从处理器分派的读取和写入操作的多个读取权利要求（RC）机器。 根据提供有缓存的存储器系统的控制逻辑，在由第一和第二RC机器处理的第一和第二读或写操作之间检测到危险。 暂停第二个RC机器，并记录特定位位置的第二个操作的地址位的一个子集。 响应于第一操作完成，在特定位位置处的第一操作的地址位的子集被广播。 然后再次请求第二个操作。
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2.发明授权Design structure for forwarding store data to loads in a pipelined processor 有权将数据转发到流水线处理器中的负载的设计结构公开(公告)号：US07752393B2
公开(公告)日：2010-07-06
申请号：US12114785
申请日：2008-05-04
申请人： Jason A. Cox , Kevin C. K. Lin , Eric F. Robinson
发明人： Jason A. Cox , Kevin C. K. Lin , Eric F. Robinson
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F12/0802
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.
摘要翻译： 提供了一种体现在用于设计，制造和/或测试用于将存储数据转发到流水线处理器中的负载的设计的机器可读存储介质中的设计结构。 在一个实现中，提供了一种处理器，其包括可解码指令的解码器和可操作以分别从解码器执行解码指令的多个执行单元。 多个执行单元包括可执行解码的加载指令和解码的存储指令并产生相应的加载存储器操作并存储存储器操作的加载/存储执行单元。 存储队列可操作以在一个或多个存储器操作完成之前缓冲一个或多个存储存储器操作，并且存储队列可操作以将缓存在存储队列中的一个或多个存储存储器操作的数据转发到负载 以逐个字节为基础的存储器操作。
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公开(公告)号：US08671247B2
公开(公告)日：2014-03-11
申请号：US12967086
申请日：2010-12-14
申请人： Jason A. Cox , Kevin C K Lin , Eric F. Robinson , Mark J. Wolski
发明人： Jason A. Cox , Kevin C K Lin , Eric F. Robinson , Mark J. Wolski
IPC分类号： G06F13/00
CPC分类号： G06F12/0833 , G06F12/0811
摘要： An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.
摘要翻译： 用于将入站总线操作传送到处理器侧处理机的L2高速缓存，方法和计算机程序产品。 该方法包括接收通过系统互连接收的入站总线操作的总线操作处理机，总线操作处理机识别将完成总线操作的处理器侧处理机的需求操作，总线操作处理机器发送所识别的需求 对处理器侧处理机进行操作，以及执行所识别的需求操作的处理器侧处理机。
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4.发明申请公开(公告)号：US20080120523A1
公开(公告)日：2008-05-22
申请号：US11561010
申请日：2006-11-17
申请人： Jason A. Cox , Keith A. DeWeese , Robert J. Dorsey , Eric F. Robinson , Thuong Q. Truong , Mark J. Wolski
发明人： Jason A. Cox , Keith A. DeWeese , Robert J. Dorsey , Eric F. Robinson , Thuong Q. Truong , Mark J. Wolski
IPC分类号： G06F11/30
CPC分类号： G06F11/3636
摘要： A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.
摘要翻译： 一种用于从非并发事件创建跟踪触发的方法和系统，所述系统包括：跟踪触发机制，包括：多个多路复用器，用于将多个信号分解成多组信号; 用于匹配多个信号以形成多个事件的模式匹配机制，以及跟踪阵列触发控制块，以对多个独立控制的事件执行一个或多个功能，以便从非并发事件创建灵活的跟踪触发控制 以控制诸如用于捕获跟踪数据的数据收集功能的启动和停止。
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5.发明申请ADDRESS-BASED HAZARD RESOLUTION FOR MANAGING READ/WRITE OPERATIONS IN A MEMORY CACHE 失效基于地址的危险解决方案，用于管理存储器高速缓存中的读/写操作公开(公告)号：US20120198178A1
公开(公告)日：2012-08-02
申请号：US13017250
申请日：2011-01-31
申请人： Jason A. Cox , Robert J. Dorsey , Kevin CK Lin , Eric F. Robinson
发明人： Jason A. Cox , Robert J. Dorsey , Kevin CK Lin , Eric F. Robinson
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0857 , Y02D10/13
摘要： One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.
摘要翻译： 一个实施例提供了一种缓存的存储器系统，其包括存储器高速缓存和被配置用于执行从处理器分派的读取和写入操作的多个读取权利要求（RC）机器。 根据提供有缓存的存储器系统的控制逻辑，在由第一和第二RC机器处理的第一和第二读或写操作之间检测到危险。 暂停第二个RC机器，并记录特定位位置的第二个操作的地址位的一个子集。 响应于第一操作完成，在特定位位置处的第一操作的地址位的子集被广播。 然后再次请求第二个操作。
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6.发明授权公开(公告)号：US07689870B2
公开(公告)日：2010-03-30
申请号：US11561010
申请日：2006-11-17
申请人： Jason A. Cox , Keith A. DeWeese , Robert J. Dorsey , Eric F. Robinson , Thuong Q. Truong , Mark J. Wolski
发明人： Jason A. Cox , Keith A. DeWeese , Robert J. Dorsey , Eric F. Robinson , Thuong Q. Truong , Mark J. Wolski
IPC分类号： G06F11/00
CPC分类号： G06F11/3636
摘要： A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.
摘要翻译： 一种用于从非并发事件创建跟踪触发的方法和系统，所述系统包括：跟踪触发机制，包括：多个多路复用器，用于将多个信号分解成多组信号; 用于匹配多个信号以形成多个事件的模式匹配机制，以及跟踪阵列触发控制块，以对多个独立控制的事件执行一个或多个功能，以便从非并发事件创建灵活的跟踪触发控制 以控制诸如用于捕获跟踪数据的数据收集功能的启动和停止。
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7.发明申请公开(公告)号：US20080091879A1
公开(公告)日：2008-04-17
申请号：US11548829
申请日：2006-10-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831
摘要： A system for breaking out of live-locks, the system including: a plurality of central processing units (CPUs), each of the plurality of CPUs having a first level cache; a plurality of second level cache, each of the plurality of second level cache in communication with one or more of the plurality of CPUs; wherein each of the plurality of second level cache includes a plurality of DMs (Data Machines); and wherein the system executes the communication between the plurality of CPUs and the plurality of second level cache by implementing the steps: randomly stopping dispatching of one or more requests; verifying that the plurality of DMs of the second level cache is in an idle state; entering into a single dispatch mode, whereby a DM is dispatched if it is determined that every DM of the second level cache is in the idle state; and returning to normal dispatch mode in a random manner.
摘要翻译： 一种用于断开实时锁定的系统，所述系统包括：多个中央处理单元（CPU），所述多个CPU中的每一个具有第一级高速缓存; 多个第二级高速缓存，所述多个第二级高速缓存中的每一个与所述多个CPU中的一个或多个通信; 其中所述多个第二级高速缓存中的每一个包括多个DM（数据机）; 并且其中所述系统通过执行以下步骤来执行所述多个CPU和所述多个第二级高速缓存之间的通信：随机地停止一个或多个请求的调度; 验证所述第二级高速缓存器的所述多个DM处于空闲状态; 进入单个调度模式，如果确定第二级高速缓存的每个DM处于空闲状态，则调度DM; 并以随机的方式返回正常的调度模式。
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公开(公告)号：US20120159086A1
公开(公告)日：2012-06-21
申请号：US12969644
申请日：2010-12-16
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses.
摘要翻译： 披露了缓存管理的方法，设备和计算机程序产品。 实施例包括由高速缓存控制器接收将新的高速缓存行插入到高速缓存中的请求; 由所述高速缓存控制器确定所述新的高速缓存行是否与强制注入相关联; 响应于确定新的高速缓存行与强制注入相关联，由高速缓存控制器接受将新的高速缓存行插入到高速缓存中; 并且响应于确定新的高速缓存行不与强制注入相关联，由高速缓存控制器基于新的高速缓存行的地址与预定义的高速缓存行的比较来确定是否接受新的高速缓存行的插入 地址范围
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公开(公告)号：US08352646B2
公开(公告)日：2013-01-08
申请号：US12969651
申请日：2010-12-16
申请人： Jason A. Cox , Omer Heymann , Nadav Levison , Kevin C. Lin , Eric F. Robinson
发明人： Jason A. Cox , Omer Heymann , Nadav Levison , Kevin C. Lin , Eric F. Robinson
IPC分类号： G06F13/28
CPC分类号： G06F12/084 , G06F12/0877 , Y02D10/13
摘要： Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.
摘要翻译： 公开了用于直接访问高速缓冲存储器的方法和装置。 实施例包括由连接到用于高速缓存存储器的高速缓存控制器的直接访问管理器接收描述要对高速缓存存储器执行的区域范围零操作的区域范围零命令; 响应于接收到区域范围零命令，生成直接存储器访问区域范围零命令，直接存储器访问区域范围零命令具有操作代码和操作所在的高速缓冲存储器的物理地址的标识 执行 将直接存储器访问区范围零命令发送到高速缓存存储器的高速缓存控制器; 并且由缓存控制器根据操作代码和高速缓冲存储器的物理地址的识别来执行直接存储器访问区域范围零操作。
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10.发明授权Ensuring forward progress of token-required cache operations in a shared cache 有权确保共享缓存中令牌所需的高速缓存操作的进展公开(公告)号：US08938588B2
公开(公告)日：2015-01-20
申请号：US12969617
申请日：2010-12-16
申请人： Jason A. Cox , Eric F. Robinson , Mark J. Wolski
发明人： Jason A. Cox , Eric F. Robinson , Mark J. Wolski
CPC分类号： G06F12/0833 , G06F12/084
摘要： Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.
摘要翻译： 确保共享缓存中令牌所需的高速缓存操作的进展，包括：侦听执行令牌所需缓存操作的指令; 确定窥探机是否可用，并且窥探机被设置为预约状态; 如果窥探机可用并且窥探机器处于预约状态，则确定执行令牌所需高速缓存操作的指令是否拥有令牌或是联合指令; 如果指令是联合指令，指示操作重试; 如果执行令牌需要的缓存操作的指令拥有一个令牌，则调度一个缓存控制器; 确定相关计算节点的所有需要的高速缓存控制器是否可用于执行指令; 如果所需的高速缓存控制器可用，则执行指令，否则不执行指令。
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