-
公开(公告)号：US20100175040A1
公开(公告)日：2010-07-08
申请号：US12350251
申请日：2009-01-08
申请人： Jason E. Meiring , Henning Haffner
发明人： Jason E. Meiring , Henning Haffner
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout.
摘要翻译： 本发明的实施例提供了一种将打印辅助特征放置在掩模布局中的方法。 该方法包括提供具有一个或多个设计特征的设计布局; 产生一组参数，该组参数与一个或多个打印辅助特征（PrAF）相关联; 将该组参数中的一个或多个PrAF添加到设计布局以产生修改的设计布局; 在修改的设计布局上执行一个或多个PrAF的模拟和一个或多个设计的特征; 基于模拟结果验证一个或多个PrAF是否可移除; 以及如果一个或多个PrAF被验证为可移除的，则基于该参数集创建一组PrAF放置规则。 PrAF放置规则的集合可以用于创建用于创建掩模布局的最后一组PrAF特征。
-
公开(公告)号：US20090081563A1
公开(公告)日：2009-03-26
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译： 公开了集成电路及其制造和设计方法。 例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。 使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。 第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。 使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。
-
公开(公告)号：US08099684B2
公开(公告)日：2012-01-17
申请号：US12350251
申请日：2009-01-08
申请人： Jason E Meiring , Henning Haffner
发明人： Jason E Meiring , Henning Haffner
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout.
摘要翻译： 本发明的实施例提供了一种将打印辅助特征放置在掩模布局中的方法。 该方法包括提供具有一个或多个设计特征的设计布局; 产生一组参数，该组参数与一个或多个打印辅助特征（PrAF）相关联; 将该组参数中的一个或多个PrAF添加到设计布局以产生修改的设计布局; 在修改的设计布局上执行一个或多个PrAF的模拟和一个或多个设计的特征; 基于模拟结果验证一个或多个PrAF是否可移除; 以及如果一个或多个PrAF被验证为可移除的，则基于该参数集创建一组PrAF放置规则。 PrAF放置规则的集合可以用于创建用于创建掩模布局的最后一组PrAF特征。
-
公开(公告)号：US08039203B2
公开(公告)日：2011-10-18
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译： 公开了集成电路及其制造和设计方法。 例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。 使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。 第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。 使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。
-
公开(公告)号：US08875063B2
公开(公告)日：2014-10-28
申请号：US12901595
申请日：2010-10-11
申请人： Zachary Baum , Scott D. Halle , Henning Haffner
发明人： Zachary Baum , Scott D. Halle , Henning Haffner
CPC分类号： G03F1/30 , G03F1/0069
摘要： A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.
摘要翻译： 描述了形成掩模布局的方法。 在具有多个关键特征的集成电路芯片的设计布局的关键特征的任一侧上形成多个相位形状。 从每个相位形状的边缘识别多个过渡边缘。 每个过渡边缘与关键特征平行。 识别由包括两个过渡边缘和一个过渡边缘的组之一所定义的过渡空间。 通过用至少一个关闭边缘关闭每个过渡空间来形成过渡多边形。 每个过渡多边形被转换成打印辅助功能。 从打印辅助功能和关键特征形成面罩布局。
-
6.发明授权L-shaped feature, method of making an L-shaped feature and method of making an L-shaped structure 有权L形特征，制作L形特征的方法和制作L形结构的方法公开(公告)号：US08426114B2
公开(公告)日：2013-04-23
申请号：US13016841
申请日：2011-01-28
申请人： Henning Haffner , Martin Ostermayr
发明人： Henning Haffner , Martin Ostermayr
IPC分类号： G03F7/00
摘要： In accordance with an embodiment of the present invention, a method for making a semiconductor device comprises forming a photo sensitive layer on a semiconductive substrate, and forming an L-shaped structure in the photo sensitive layer by exposing the photo sensitive layer to light via a reticle, wherein the reticle comprises an L-shapes feature having a first non-orthogonal edge at an intersection of two legs of the L-shaped feature.
摘要翻译： 根据本发明的实施例，制造半导体器件的方法包括在半导体衬底上形成感光层，并且通过经由光敏层曝光光敏层而在光敏层中形成L形结构 掩模版，其中所述标线片包括在所述L形特征的两条腿的交叉处具有第一非正交边缘的L形特征。
-
公开(公告)号：US08365108B2
公开(公告)日：2013-01-29
申请号：US12985643
申请日：2011-01-06
摘要： Aspects of the invention include a computer-implemented method of designing a photomask. In one embodiment, the method comprises: simulating a first photomask patterning process using a first photomask design to create simulated contours; comparing the simulated contours to a desired design; identifying regions not common to the simulated contours and the desired design; creating desired target shapes for a second photomask patterning process subsequent to the first photomask patterning process based upon the identified regions; and providing the desired target shapes for forming of a second photomask design based upon the desired target shapes.
摘要翻译： 本发明的方面包括设计光掩模的计算机实现的方法。 在一个实施例中，该方法包括：使用第一光掩模设计来模拟第一光掩模图案化工艺以产生模拟轮廓; 将模拟轮廓与期望的设计进行比较; 识别不同于模拟轮廓和所需设计的区域; 在基于所识别的区域的第一光掩模图案化工艺之后，为第二光掩模图案化工艺创建期望的目标形状; 以及基于期望的目标形状提供用于形成第二光掩模设计的期望的目标形状。
-
公开(公告)号：US20120074499A1
公开(公告)日：2012-03-29
申请号：US13296578
申请日：2011-11-15
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译： 公开了集成电路及其制造和设计方法。 例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。 第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。 基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。 该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。
-
公开(公告)号：US20100276759A1
公开(公告)日：2010-11-04
申请号：US12839750
申请日：2010-07-20
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/088 , H01L27/02 , G06F17/50 , H01L21/64
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译： 公开了集成电路及其制造和设计方法。 例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。 第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。 基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。 该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。
-
公开(公告)号：US20100042967A1
公开(公告)日：2010-02-18
申请号：US12191493
申请日：2008-08-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the result of an effectively overall lowered MEEF) to produce a pattern on wafer that is circular to within an acceptable tolerance.
摘要翻译： 一种意图放松OPC算法约束以允许OPC掩模形状沿着一个方向伸长的方法（特别是在该方向上降低1维MEEF，结果是有效地降低了MEEF），从而在晶圆上产生一个圆形到 在可接受的容限内。
-
-
-
-
-
-
-
-
-
搜索结果
65 条记录 (耗时 0.024 秒)
