公开(公告)号：US20050096862A1

公开(公告)日：2005-05-05

申请号：US10605884

申请日：2003-11-04

申请人： Jason Norman ,  Nancy Pratt ,  Sebastian Ventrone

发明人： Jason Norman ,  Nancy Pratt ,  Sebastian Ventrone

IPC分类号： G01R31/14 ,  G06F11/26

CPC分类号： G06F11/261

摘要： A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.

摘要翻译： 用于识别构成虚拟机的逻辑功能区域受到特定测试用例影响的方法和系统。 硬件描述符语言（HDL）用于创建虚拟机的软件模型。 模拟器编译和分析HDL模型，并创建一个标识虚拟机中逻辑功能区域的矩阵记分板。 测试用例的完整列表在虚拟机上运行，​​而监视器将每个测试用例与受影响的逻辑功能区域相关联，以填充矩阵记分板。 当随后的测试失败发生时，由于对逻辑功能区域的修改或新测试的执行，所有被直接或间接影响的逻辑功能区域都被识别。

公开(公告)号：US20080068073A1

公开(公告)日：2008-03-20

申请号：US11937559

申请日：2007-11-09

申请人： Nancy Pratt ,  Sebastian Ventrone

发明人： Nancy Pratt ,  Sebastian Ventrone

IPC分类号： H03K5/00

CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

公开(公告)号：US20070288787A1

公开(公告)日：2007-12-13

申请号：US11836827

申请日：2007-08-10

申请人： Nancy Pratt ,  Sebastian Ventrone

发明人： Nancy Pratt ,  Sebastian Ventrone

IPC分类号： G06F1/00

CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

公开(公告)号：US20070028151A1

公开(公告)日：2007-02-01

申请号：US11161330

申请日：2005-07-29

申请人： Laura Miller ,  Nancy Pratt ,  Sebastian Ventrone

发明人： Laura Miller ,  Nancy Pratt ,  Sebastian Ventrone

IPC分类号： G06F11/00

CPC分类号： G06F9/462 ,  G06F9/4843

摘要： A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

摘要翻译： 一种用于在单个集成电路上支持同时操作操作系统的方法和系统。 该系统包括管理指令的执行的监控操作系统（SOS），每个指令可在一个操作系统下执行; 寄存器分组成多组寄存器，每组寄存器保持一个操作系统的标识; 以及调度器，其能够分派附加到所述指令的指令和标签，所述标签识别所述操作系统中的一个以及在所述操作系统下执行的指令以访问所述寄存器之一。 当执行指令时，使用一个或多个寄存器，并且被包括在多组寄存器的单组中。 单一集合维护由标签识别的操作系统的标识，并且一个或多个寄存器中的每一个包括与标签相匹配的标识符。

公开(公告)号：US20060082398A1

公开(公告)日：2006-04-20

申请号：US11275773

申请日：2006-01-27

申请人： Nancy Pratt ,  Sebastian Ventrone

发明人： Nancy Pratt ,  Sebastian Ventrone

IPC分类号： H03B21/00

CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

公开(公告)号：US20060262779A1

公开(公告)日：2006-11-23

申请号：US10908597

申请日：2005-05-18

申请人： Adam Courchesne ,  Kenneth Goodnow ,  W. Harding ,  David Milton ,  Jason Norman ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

发明人： Adam Courchesne ,  Kenneth Goodnow ,  W. Harding ,  David Milton ,  Jason Norman ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

IPC分类号： H04L12/50

CPC分类号： G06F15/7825

摘要： A method and apparatus for providing communication between various cores located in an integrated circuit. The method and apparatus uses Hubs/Routers to facilitate and manage communication of data from/between the cores according to a specified methodology.

摘要翻译： 一种用于提供位于集成电路中的各种核心之间的通信的方法和装置。 该方法和装置使用集线器/路由器来根据指定的方法来促进和管理来自/在核心之间的数据的通信。

公开(公告)号：US20050076170A1

公开(公告)日：2005-04-07

申请号：US10680756

申请日：2003-10-07

申请人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

发明人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F13/4269

摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.

摘要翻译： 一种用于控制半导体器件上的数据流的结构和相关方法。 在半导体器件内形成发射器，接收器和传输线。 发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。 发射机适于通过传输线路将信号发送到适于接收信号的接收机。 接收机还适于产生阻抗失配以指示第二核心不能传送数据。 发射机适用于检测阻抗失配。

公开(公告)号：US20050013527A1

公开(公告)日：2005-01-20

申请号：US10604410

申请日：2003-07-18

申请人： Gary Doyle ,  Kenneth Goodnow ,  Riyon Harding ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

发明人： Gary Doyle ,  Kenneth Goodnow ,  Riyon Harding ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： G02B6/43 ,  G02B6/12 ,  G02B6/26

CPC分类号： G02B6/43

摘要： Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

摘要翻译： 公开了一种集成电路，其包括附接到至少一个发射机和接收机的多个核心，嵌入在集成电路的有线电平内的光传输网络，并且其中发射机和接收机在网络上发送和接收数据。 还公开了一种在包括多个核心和光路的集成电路的集成电路内传输信号的方法，从多个光路中选择用于发送数据的光路，以及在所选择的光路上发送数据。 还公开了一种集成电路，其包括光传输网络，多个核心和多个控制器，所有三个可操作地彼此连接。

公开(公告)号：US20060189294A1

公开(公告)日：2006-08-24

申请号：US11410829

申请日：2006-04-24

申请人： Kenneth Goodnow ,  Riyon Harding ,  Charles Masenas ,  Jason Norman ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Riyon Harding ,  Charles Masenas ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： H04B1/28

CPC分类号： H04B1/38

摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

摘要翻译： 一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。 通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。 发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。 每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。 核心组可以共享发射机和接收机电路。

公开(公告)号：US20050071575A1

公开(公告)日：2005-03-31

申请号：US10605366

申请日：2003-09-25

申请人： Kenneth Goodnow ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0284

摘要： A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

摘要翻译： 一种半导体器件上传输数据的结构和相关方法，包括：半导体器件内的多个系统。 每个系统包括至少一个处理设备和本地存储器结构。 每个处理设备电耦合到每个系统内的每个本地存储器结构。 每个本地存储器结构电耦合到每个其他所述本地存储器结构。 每个本地存储器结构适于与每个处理设备共享地址空间。 每个处理设备适于将数据和指令传送到每个本地存储器结构。