公开(公告)号：US20050013527A1

公开(公告)日：2005-01-20

申请号：US10604410

申请日：2003-07-18

申请人： Gary Doyle ,  Kenneth Goodnow ,  Riyon Harding ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

发明人： Gary Doyle ,  Kenneth Goodnow ,  Riyon Harding ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： G02B6/43 ,  G02B6/12 ,  G02B6/26

CPC分类号： G02B6/43

摘要： Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

摘要翻译： 公开了一种集成电路，其包括附接到至少一个发射机和接收机的多个核心，嵌入在集成电路的有线电平内的光传输网络，并且其中发射机和接收机在网络上发送和接收数据。 还公开了一种在包括多个核心和光路的集成电路的集成电路内传输信号的方法，从多个光路中选择用于发送数据的光路，以及在所选择的光路上发送数据。 还公开了一种集成电路，其包括光传输网络，多个核心和多个控制器，所有三个可操作地彼此连接。

公开(公告)号：US20060189294A1

公开(公告)日：2006-08-24

申请号：US11410829

申请日：2006-04-24

申请人： Kenneth Goodnow ,  Riyon Harding ,  Charles Masenas ,  Jason Norman ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Riyon Harding ,  Charles Masenas ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： H04B1/28

CPC分类号： H04B1/38

摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

摘要翻译： 一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。 通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。 发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。 每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。 核心组可以共享发射机和接收机电路。

公开(公告)号：US20050071575A1

公开(公告)日：2005-03-31

申请号：US10605366

申请日：2003-09-25

申请人： Kenneth Goodnow ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0284

摘要： A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

摘要翻译： 一种半导体器件上传输数据的结构和相关方法，包括：半导体器件内的多个系统。 每个系统包括至少一个处理设备和本地存储器结构。 每个处理设备电耦合到每个系统内的每个本地存储器结构。 每个本地存储器结构电耦合到每个其他所述本地存储器结构。 每个本地存储器结构适于与每个处理设备共享地址空间。 每个处理设备适于将数据和指令传送到每个本地存储器结构。

公开(公告)号：US20060262779A1

公开(公告)日：2006-11-23

申请号：US10908597

申请日：2005-05-18

申请人： Adam Courchesne ,  Kenneth Goodnow ,  W. Harding ,  David Milton ,  Jason Norman ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

发明人： Adam Courchesne ,  Kenneth Goodnow ,  W. Harding ,  David Milton ,  Jason Norman ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

IPC分类号： H04L12/50

CPC分类号： G06F15/7825

摘要： A method and apparatus for providing communication between various cores located in an integrated circuit. The method and apparatus uses Hubs/Routers to facilitate and manage communication of data from/between the cores according to a specified methodology.

摘要翻译： 一种用于提供位于集成电路中的各种核心之间的通信的方法和装置。 该方法和装置使用集线器/路由器来根据指定的方法来促进和管理来自/在核心之间的数据的通信。

公开(公告)号：US20080030226A1

公开(公告)日：2008-02-07

申请号：US11869921

申请日：2007-10-10

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： H03K19/173

CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

公开(公告)号：US20070258305A1

公开(公告)日：2007-11-08

申请号：US11279639

申请日：2006-04-13

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F12/122

摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

公开(公告)号：US20050251778A1

公开(公告)日：2005-11-10

申请号：US11181053

申请日：2005-07-14

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone

IPC分类号： G06F15/78 ,  H03K19/177 ,  H03K19/00

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

摘要翻译： 一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。 需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。 程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

公开(公告)号：US20070228830A1

公开(公告)日：2007-10-04

申请号：US11278262

申请日：2006-03-31

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

IPC分类号： H02J3/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  H01L25/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  Y02D10/171 ,  Y10T307/391

摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.

摘要翻译： 一种降低低功率电子设备中的静态功耗的方法。 所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的相应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

公开(公告)号：US20070075733A1

公开(公告)日：2007-04-05

申请号：US11162997

申请日：2005-09-30

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： H03K19/177

CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

摘要翻译： 包括基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）装置。 非基于编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而节省加电时的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和齐平扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

公开(公告)号：US20050125749A1

公开(公告)日：2005-06-09

申请号：US10707323

申请日：2003-12-05

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Jack Smith ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Jack Smith ,  Sebastian Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F11/18

摘要： A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the operator “FT” to certain logic functions. Logic functions that include the FT operator are considered critical functions, i.e., fault tolerant. By including the FT operator, a logic synthesis tool is alerted to the functions that have been designated as fault tolerant. As a result, the preprogrammed logic synthesis tool causes the design of the IC to include a fault redundant scheme (30) for the logic functions that include the FT operator. Fault redundant scheme (30) includes three copies of the logic function, i.e., Copy A (32), Copy B (34), and Copy C (36), as well as a majority voter 38.

摘要翻译： 用于指定特定逻辑功能作为容错的寄存器传输级（RTL）的新硬件描述语言（HDL）扩展以及为容错逻辑功能实现故障冗余方案的方法。 代码（20）以RTL写入VHDL，并包括将操作符“FT”添加到某些逻辑功能的指令。 包括FT操作员的逻辑功能被认为是关键功能，即容错。 通过包括FT操作员，逻辑综合工具被提醒已被指定为容错的功能。 因此，预编程的逻辑综合工具使得IC的设计包括用于包括FT操作员的逻辑功能的故障冗余方案（30）。 故障冗余方案（30）包括逻辑功能的三个副本，即复制A（32），复制B（34）和复制C（36）以及多数选民38。