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1.发明授权公开(公告)号：US07402529B2
公开(公告)日：2008-07-22
申请号：US11139143
申请日：2005-05-26
申请人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
发明人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
IPC分类号： H01L21/302
CPC分类号： G11C11/16 , H01L27/222
摘要： A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
摘要翻译： 制造用于MRAM器件的包层区域的方法包括形成靠近磁阻存储器件的导电位线。 将导电位线浸入包含第一导电材料的溶解离子的第一槽中足以使导电线上的第一阻挡层移位的时间。 然后将第一阻挡层浸入无电镀浴中以在第一阻挡层上形成通量聚集层。 将集流层浸入含有第二导电材料的溶解离子的第二槽中，持续足够的时间使得在集流层上移动第二阻挡层。
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公开(公告)号：US06927072B2
公开(公告)日：2005-08-09
申请号：US10093909
申请日：2002-03-08
申请人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
发明人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
IPC分类号： H01L27/105 , C25D5/12 , G11C11/15 , G11C11/16 , H01L21/00 , H01L21/4763 , H01L21/8246 , H01L27/22
CPC分类号： G11C11/16 , H01L27/222
摘要： A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
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公开(公告)号：US06888743B2
公开(公告)日：2005-05-03
申请号：US10331058
申请日：2002-12-27
申请人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
发明人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
CPC分类号： G11C11/16
摘要： An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
摘要翻译： 提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。 组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。 优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。
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4.发明授权Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers 失效用于使用多个磁性层编程MRAM器件的导电互连的包层公开(公告)号：US06720597B2
公开(公告)日：2004-04-13
申请号：US10010363
申请日：2001-11-13
IPC分类号： H01L2976
CPC分类号： H01L27/222 , G11C11/16
摘要： A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.
摘要翻译： 一种用于编程磁阻存储器件的包覆导电互连件，其包括具有长度的导电材料，位于导电材料上的第一阻挡导电材料，以及沿导电材料的长度定位的多层包覆区域，其中多层 包层区域包括N个铁磁层，其中N是大于或等于2的整数，并且其中所述多层包覆区域还包括至少一个间隔层，其中所述间隔层可以包括金属，绝缘体或 交换相互作用材料，并且其中间隔层夹在每个相邻的铁磁层之间。
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5.发明授权Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer 失效磁性随机存取存储器具有带铁磁覆层的数字线和位线公开(公告)号：US06430084B1
公开(公告)日：2002-08-06
申请号：US09940263
申请日：2001-08-27
IPC分类号： G11C1115
CPC分类号： G11C11/5607 , G11C11/16 , H01L27/222
摘要： A magneto-electronic component includes an electrically conductive layer for generating a magnetic field, a ferromagnetic cladding layer adjacent to the electrically conductive layer, and an antiferromagnetic layer adjacent to the ferromagnetic cladding layer.
摘要翻译： 磁电子部件包括用于产生磁场的导电层，与导电层相邻的铁磁性包层，以及与铁磁性包覆层相邻的反铁磁层。
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公开(公告)号：US07235408B2
公开(公告)日：2007-06-26
申请号：US11075587
申请日：2005-03-09
IPC分类号： H01L21/00
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G01R33/093 , G11C11/16 , H01F10/3254 , H01F10/3272 , H01F41/302 , H01L43/12
摘要： A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.
摘要翻译： 可以有利地用于诸如磁阻存储器单元的磁电子器件中的几乎平衡的合成反铁磁（SAF）结构包括两个铁磁层和分离两个铁磁层的反铁磁耦合层。 SAF自由层通过诸如退火，反铁磁耦合层的分层或在铁磁层的粗糙表面上形成反铁磁耦合层的处理，在反铁磁耦合层中形成弱耦合区域。 与未处理的SAF自由层相比，弱耦合区域降低了SAF自由层的触发场。 在这种结构的写入操作期间使用SAF触发器，并且其减少导致在写入操作期间较低的功耗并且相应地增加器件性能。
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公开(公告)号：US06531723B1
公开(公告)日：2003-03-11
申请号：US09978860
申请日：2001-10-16
IPC分类号： H01L31072
CPC分类号： B82Y25/00 , B82Y40/00 , G11C11/15 , G11C11/16 , H01F10/3254 , H01F10/3268 , H01F41/302 , H01L43/08
摘要： A scalable magnetoresistive tunneling junction memory cell comprising a fixed ferromagnetic region having a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, an electrically insulating material positioned on the fixed ferromagnetic region to form a magnetoresistive tunneling junction, and a free ferromagnetic region having a magnetic moment vector oriented in a position parallel or anti-parallel to that of the fixed ferromagnetic region. The free ferromagnetic region includes N ferromagnetic layers that are anti-ferromagnetically coupled, where N is an integer greater than or equal to two. The number N of ferromagnetic layers can be adjusted to increase the effective magnetic switching volume of the MRAM device.
摘要翻译： 一种可扩展的磁阻隧道结存储单元，包括在没有施加的磁场的情况下具有固定在优选方向上的磁矩向量的固定铁磁区域，位于固定铁磁区上的电绝缘材料以形成磁阻隧道结，以及 具有定向在与固定铁磁性区域平行或反平行的位置的磁矩矢量的自由铁磁区域。 自由铁磁区域包括反铁磁耦合的N个铁磁层，其中N是大于或等于2的整数。 可以调节铁磁层数N，以增加MRAM器件的有效磁开关量。
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公开(公告)号：US07129098B2
公开(公告)日：2006-10-31
申请号：US10997118
申请日：2004-11-24
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , H01L27/222 , H01L43/08
摘要： Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin≈(Hsat−Nσsat)−(Hsw+Nσsw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW≅√{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.
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公开(公告)号：US06909631B2
公开(公告)日：2005-06-21
申请号：US10679134
申请日：2003-10-02
申请人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
发明人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
摘要： An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.
摘要翻译： 提供了一种MRAM，其通过利用每个存储单元中的隔离或选择装置来最小化MRAM密度的限制。 另外，提供了用于读取MRAM的联动存储单元中的MTJ的方法。 该方法包括确定至少部分地与MRAM的联动存储器单元的电阻相关联的电气值。 切换联合存储器单元中的MTJ，并且在切换MTJ之后确定至少部分地与组合存储器单元的电阻相关联的第二电值。 一旦确定了切换之前和切换之后的电气值，则分析两个电气值之间的差异，以确定MTJ的值。
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公开(公告)号：US07329935B2
公开(公告)日：2008-02-12
申请号：US11581951
申请日：2006-10-16
CPC分类号： G11C11/16 , H01L27/222 , H01L43/08
摘要： Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin≈(Hsat−σsat)−(Hsw+σsw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW≅√{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.
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