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1.发明授权公开(公告)号：US07386815B2
公开(公告)日：2008-06-10
申请号：US11163696
申请日：2005-10-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。
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2.发明授权公开(公告)号：US08010916B2
公开(公告)日：2011-08-30
申请号：US12062586
申请日：2008-04-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。
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公开(公告)号：US20080189664A1
公开(公告)日：2008-08-07
申请号：US12062586
申请日：2008-04-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。
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公开(公告)号：US20070099236A1
公开(公告)日：2007-05-03
申请号：US11163696
申请日：2005-10-27
申请人： Jeanne Bickford , Markus Buehler , Jason Hibbeler , Juergen Koehl
发明人： Jeanne Bickford , Markus Buehler , Jason Hibbeler , Juergen Koehl
IPC分类号： C40B30/02
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。
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公开(公告)号：US20070240090A1
公开(公告)日：2007-10-11
申请号：US11279262
申请日：2006-04-11
CPC分类号： G06F17/5077
摘要： Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.
摘要翻译： 本文的实施例提供了一种用于优化路由器设置以增加IC产量的方法和计算机程序产品。 一种方法开始于检查IC生产线中的产量数据，以确定影响IC产量的结构特异性机制。 接下来，该方法为每个结构特定机制建立结构标识符，其中结构标识符包括有线代码，标签和/或唯一标识符。 针对具有不同宽度的电线建立了不同的结构标识符。 此外，该方法为每个结构特定机构建立加权因子，其中针对包括靠近多个粗线的粗线的结构特定机构建立较高的加权因子。 该方法建立了单宽线，双宽线和三宽线之间的间距发生的结构标识符和加权因子，以及大金属土地上电线的入射。 随后，路由器设置基于结构标识符和权重因子进行修改，以最大限度地减少系统缺陷。
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6.发明申请METHOD FOR COMPUTING THE SENSITIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL 失效使用关键区域分析工具计算VLSI设计对两个随机和系统缺陷的灵敏度的方法公开(公告)号：US20070240085A1
公开(公告)日：2007-10-11
申请号：US11279300
申请日：2006-04-11
申请人： Jeanne Bickford , Jason Hibbeler , Juergen Koehl
发明人： Jeanne Bickford , Jason Hibbeler , Juergen Koehl
CPC分类号： G06F17/5081
摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.
摘要翻译： 估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。 接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。 更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预先扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时预结构。 接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。 然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。 随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。
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7.发明申请A METHOD , APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION 失效一种用于半导体器件估计的方法，装置和计算机程序产品公开(公告)号：US20070143720A1
公开(公告)日：2007-06-21
申请号：US11275275
申请日：2005-12-21
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.
摘要翻译： 一种方法，装置和计算机程序产品，其使用具有冗余和非冗余元件的集成电路上的关键区域分析来执行产量估计。 非冗余元素将被忽略或从对不需要的打开执行的关键区域分析中移除。
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公开(公告)号：US10067184B2
公开(公告)日：2018-09-04
申请号：US13294243
申请日：2011-11-11
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/317
摘要： A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.
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9.发明申请METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效通过调节选择性电压激活切割点来优化功率的方法公开(公告)号：US20090228843A1
公开(公告)日：2009-09-10
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.
摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。 该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。 然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。
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公开(公告)号：US20130124133A1
公开(公告)日：2013-05-16
申请号：US13294243
申请日：2011-11-11
IPC分类号： G06F19/00
CPC分类号： G01R31/31718
摘要： A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.
摘要翻译： 一种用于电压组合集成电路芯片的方法，测试系统和计算机程序产品和系统。 该方法包括使用集成电路芯片的数据路径的功能测试来选择或改变集成电路芯片的电压仓。
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