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公开(公告)号：US06385747B1
公开(公告)日：2002-05-07
申请号：US09212314
申请日：1998-12-14
IPC分类号： G11C2900
摘要： A technique is provided for use in testing replicated components (e.g., identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test inputs may be broadcast, in parallel, from a single test interface to each of the replicated components of the electronic device under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the electronic device, that compares the respective test outputs to each other and generates a fault signal if corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface, and its assertion may indicate that one or more of the replicated components may be defective. The respective test outputs may be multiplexed to permit output via an external interface of respective test outputs from a selected component. These respective test outputs may be compared to expected values therefor whereby to determine presence and/or nature of defects in the replicated components.
摘要翻译： 提供了用于测试用于缺陷的电子设备的复制组件（例如，相同的电路组件）的技术。 在该测试技术的一个方面，相同的测试输入可以并行地从单个测试接口广播到被测试的电子设备的每个复制组件。 响应于测试输入而由复制组件生成的各个测试输出可以被提供给包括在电子设备中的比较器，其将相应的测试输出彼此进行比较，并且如果相应的测试输出不相同则产生故障信号。 该故障信号可以被提供给单个测试接口的外部测试接口引脚，并且其断言可以指示一个或多个复制部件可能是有缺陷的。 相应的测试输出可以被多路复用以允许经由所选择的组件的相应测试输出的外部接口的输出。 这些各自的测试输出可以与期望值进行比较，从而确定复制组件中的缺陷的存在和/或性质。
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公开(公告)号：US06173386B2
公开(公告)日：2001-01-09
申请号：US09213291
申请日：1998-12-14
IPC分类号： G06F1516
CPC分类号： G06F11/3648
摘要： A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
摘要翻译： 提供并行处理器，包括集成的调试功能。 处理器包括流水线处理引擎，具有处理元件复杂级的阵列，以及输入和输出头缓冲器。 提供了一种调试系统，当被触发时，可以将部分或全部处理元件复合体置于调试操作模式中。 当复合体处于调试模式时，可能会发现复合体的组件电路的内部级的检查，以便于调试在处理器运行期间可能发生的软件和硬件错误。
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3.发明授权公开(公告)号：US06876961B1
公开(公告)日：2005-04-05
申请号：US09384504
申请日：1999-08-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A technique is provided for use in computerized modeling of an electronic system. The technique bases simulation of the system's operation (e.g., timing operation) upon both actual physical characteristics of a part of the system, and hierarchical analysis-based models of the rest of the system.
摘要翻译： 提供了一种用于电子系统的计算机化建模的技术。 该技术基于系统的一部分的实际物理特性和系统的其余部分的基于分析的分析模型来对系统的操作（例如，定时操作）进行模拟。
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4.发明授权Pooled receive and transmit queues to access a shared bus in a multi-port switch asic 失效汇集接收和发送队列以访问多端口交换机中的共享总线公开(公告)号：US06356548B1
公开(公告)日：2002-03-12
申请号：US09106245
申请日：1998-06-29
IPC分类号： H04L1240
CPC分类号： H04L49/102 , H04L49/205 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04Q11/04 , H04Q2213/13003 , H04Q2213/13056 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/1334 , H04Q2213/13341
摘要： A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.
摘要翻译： 多端口交换设备架构将网络交换机的每个端口的解码逻辑电路与其相应的状态机逻辑电路分离，并将状态机逻辑组织为由每个解码逻辑电路共享的发送/接收引擎资源池。 交换设备的中间优先级逻辑与解码逻辑和汇集的资源协调，以根据预定的排序和公平策略在可用资源之间分配帧。 这些策略可防止框架从单一来源错误排列，同时确保设备中的所有端口都能公平地进行维护。
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5.发明授权System for context switching between processing elements in a pipeline of processing elements 失效用于处理元素流水线中处理元素之间的上下文切换的系统
公开(公告)号：US6101599A
公开(公告)日：2000-08-08
申请号：US106244
申请日：1998-06-29
CPC分类号： G06F9/461 , G06F15/17381 , G06F9/30123 , H04L49/251 , H04L49/3063
摘要： A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core having a plurality of internal context switchable registers that are connected to respective registers within CPU cores of the pipelined stages by a processor bus. The technique enables fast context switching by sharing the context switchable registers between upstream and downstream CPUs to, inter alia, force program counters into the downstream registers. In one aspect of the inventive technique, the system automatically reflects (shadows) the contents of an upstream CPU's context switchable registers at respective registers of a downstream CPU over the processor bus. In another aspect of the invention, the system redirects instruction execution by the downstream CPU to an appropriate routine based on processing performed by the upstream CPU.
摘要翻译： 一种系统和技术有助于在流水线处理引擎的处理器复杂阶段之间进行快速上下文切换。 每个处理器复合体包括具有多个内部上下文可切换寄存器的中央处理单元（CPU）核心，其通过处理器总线连接到流水线级的CPU核心内的相应寄存器。 该技术通过在上游和下游CPU之间共享上下文可切换寄存器来实现快速上下文切换，特别是将程序计数器强制到下游寄存器中。 在本发明技术的一个方面，系统通过处理器总线自动反映（阴影）上游CPU上下文切换寄存器的内容到下游CPU的相应寄存器。 在本发明的另一方面，系统基于上游CPU执行的处理将下游CPU的指令执行重定向到适当的例程。
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6.发明授权公开(公告)号：US06442669B2
公开(公告)日：2002-08-27
申请号：US09727068
申请日：2000-11-30
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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7.发明授权Method and apparatus for passing data among processor complex stages of a pipelined processing engine 失效用于在流水线处理引擎的处理器复杂级之间传递数据的方法和装置公开(公告)号：US06195739B1
公开(公告)日：2001-02-27
申请号：US09106436
申请日：1998-06-29
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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公开(公告)号：US07185224B1
公开(公告)日：2007-02-27
申请号：US10731971
申请日：2003-12-10
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
摘要翻译： 处理器隔离技术增强了多处理器电路中的调试能力。 旁路寄存器具有可以指示处理器被旁路的位置。 选择代码入口点以允许下游处理器执行旁路处理器的工作。 处理器可以排列在管道中。
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9.发明授权Architecture for a processor complex of an arrayed pipelined processing engine 有权用于处理器阵列的流水线处理引擎的架构公开(公告)号：US06836838B1
公开(公告)日：2004-12-28
申请号：US10222277
申请日：2002-08-16
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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10.发明授权公开(公告)号：US06513108B1
公开(公告)日：2003-01-28
申请号：US09106478
申请日：1998-06-29
IPC分类号： G06F1516
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译： 可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。 引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。 外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。 每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。
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