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1.发明授权Pooled receive and transmit queues to access a shared bus in a multi-port switch asic 失效汇集接收和发送队列以访问多端口交换机中的共享总线公开(公告)号：US06356548B1
公开(公告)日：2002-03-12
申请号：US09106245
申请日：1998-06-29
IPC分类号： H04L1240
CPC分类号： H04L49/102 , H04L49/205 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04Q11/04 , H04Q2213/13003 , H04Q2213/13056 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/1334 , H04Q2213/13341
摘要： A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.
摘要翻译： 多端口交换设备架构将网络交换机的每个端口的解码逻辑电路与其相应的状态机逻辑电路分离，并将状态机逻辑组织为由每个解码逻辑电路共享的发送/接收引擎资源池。 交换设备的中间优先级逻辑与解码逻辑和汇集的资源协调，以根据预定的排序和公平策略在可用资源之间分配帧。 这些策略可防止框架从单一来源错误排列，同时确保设备中的所有端口都能公平地进行维护。
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2.发明授权公开(公告)号：US06876961B1
公开(公告)日：2005-04-05
申请号：US09384504
申请日：1999-08-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A technique is provided for use in computerized modeling of an electronic system. The technique bases simulation of the system's operation (e.g., timing operation) upon both actual physical characteristics of a part of the system, and hierarchical analysis-based models of the rest of the system.
摘要翻译： 提供了一种用于电子系统的计算机化建模的技术。 该技术基于系统的一部分的实际物理特性和系统的其余部分的基于分析的分析模型来对系统的操作（例如，定时操作）进行模拟。
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公开(公告)号：US06385747B1
公开(公告)日：2002-05-07
申请号：US09212314
申请日：1998-12-14
IPC分类号： G11C2900
摘要： A technique is provided for use in testing replicated components (e.g., identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test inputs may be broadcast, in parallel, from a single test interface to each of the replicated components of the electronic device under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the electronic device, that compares the respective test outputs to each other and generates a fault signal if corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface, and its assertion may indicate that one or more of the replicated components may be defective. The respective test outputs may be multiplexed to permit output via an external interface of respective test outputs from a selected component. These respective test outputs may be compared to expected values therefor whereby to determine presence and/or nature of defects in the replicated components.
摘要翻译： 提供了用于测试用于缺陷的电子设备的复制组件（例如，相同的电路组件）的技术。 在该测试技术的一个方面，相同的测试输入可以并行地从单个测试接口广播到被测试的电子设备的每个复制组件。 响应于测试输入而由复制组件生成的各个测试输出可以被提供给包括在电子设备中的比较器，其将相应的测试输出彼此进行比较，并且如果相应的测试输出不相同则产生故障信号。 该故障信号可以被提供给单个测试接口的外部测试接口引脚，并且其断言可以指示一个或多个复制部件可能是有缺陷的。 相应的测试输出可以被多路复用以允许经由所选择的组件的相应测试输出的外部接口的输出。 这些各自的测试输出可以与期望值进行比较，从而确定复制组件中的缺陷的存在和/或性质。
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公开(公告)号：US06173386B2
公开(公告)日：2001-01-09
申请号：US09213291
申请日：1998-12-14
IPC分类号： G06F1516
CPC分类号： G06F11/3648
摘要： A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
摘要翻译： 提供并行处理器，包括集成的调试功能。 处理器包括流水线处理引擎，具有处理元件复杂级的阵列，以及输入和输出头缓冲器。 提供了一种调试系统，当被触发时，可以将部分或全部处理元件复合体置于调试操作模式中。 当复合体处于调试模式时，可能会发现复合体的组件电路的内部级的检查，以便于调试在处理器运行期间可能发生的软件和硬件错误。
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公开(公告)号：US06965615B1
公开(公告)日：2005-11-15
申请号：US09663777
申请日：2000-09-18
CPC分类号： H04L49/3072 , H04L49/25 , H04L49/3063
摘要： A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.
摘要翻译： 提供了一种技术，用于在网络交换机内的处理引擎的管道上分条分组。 处理引擎包括多个处理器，其排列成嵌入在发动机的输入和输出缓冲器之间的管线行和列。 每个管道行或群集包括具有多个定义大小的窗口缓冲器的上下文存储器。 每个数据包被分配到与上下文存储器的每个缓冲器相关联的定义的窗口大小相对应的固定大小的上下文中。 该技术包括用于将每个上下文与分组内的相对位置（即，分组的开始，中间和结束上下文）相关联的映射机制。 映射机制有助于在输出缓冲器处重新组合分组，同时避免涉及分组的特定上下文的任何无序的问题。
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6.发明授权公开(公告)号：US06804815B1
公开(公告)日：2004-10-12
申请号：US09663775
申请日：2000-09-18
IPC分类号： G06F946
CPC分类号： H04L49/9094 , H04L49/90
摘要： A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.
摘要翻译： 序列控制机制使具有排列为处理引擎的多个处理器的对称多处理器系统的处理器对上下文进行无序处理。 引擎的处理器优选地被布置为嵌入在输入和输出缓冲器之间的多个行或群集，其中每个处理器群集被配置为以先进先出（FIFO）同步顺序处理上下文。 然而，序列控制机制允许处理器群集之间的无序上下文处理，同时在需要的基础上选择性地执行这些簇之间的FIFO同步排序，即对某些上下文。 结果，控制机制减少了这些处理器之间的不期望的处理延迟。
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