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公开(公告)号：US20120181549A1
公开(公告)日：2012-07-19
申请号：US13009029
申请日：2011-01-19
IPC分类号： H01L29/161 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
摘要翻译： 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。
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公开(公告)号：US08361847B2
公开(公告)日：2013-01-29
申请号：US13009029
申请日：2011-01-19
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
摘要翻译： 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。
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3.发明授权Electrical fuses comprising thin film transistors (TFTS), and methods for programming same 有权包括薄膜晶体管（TFTS）的电熔丝及其编程方法公开(公告)号：US07436044B2
公开(公告)日：2008-10-14
申请号：US11306597
申请日：2006-01-04
IPC分类号： H01L29/00
CPC分类号： H01L29/42384 , H01L23/345 , H01L23/5256 , H01L29/78669 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated thin film transistor so as to cause at least partial dehydrogenation. Consequentially, the thin film transistor exhibits detectible physical property change(s), which defines a programmed state. In an alternative embodiment of the present invention, the electrical fuse comprises a thin film transistor that is either hydrogenated or not hydrogenated. Programming of such an alternative electrical fuse can be effectuated by applying a sufficient high back gate voltage to the thin film transistor to cause state changes in the channel-gate interface. In this manner, the thin film transistor also exhibits detectible property change(s) to define a programmed state.
摘要翻译： 本发明涉及电熔丝，每个电熔丝包括至少一个薄膜晶体管。 在一个实施例中，本发明的电熔丝包括具有相邻加热元件的氢化薄膜晶体管。 可以通过加热氢化薄膜晶体管来实现这种电熔丝的编程，从而至少部分脱氢。 因此，薄膜晶体管表现出可检测的物理特性变化，其定义了编程状态。 在本发明的替代实施例中，电熔丝包括被氢化或未氢化的薄膜晶体管。 可以通过向薄膜晶体管施加足够的高背栅电压来引起通道栅极界面的状态变化来实现这种替代电熔丝的编程。 以这种方式，薄膜晶体管还具有可检测的特性变化以限定编程状态。
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公开(公告)号：US07977712B2
公开(公告)日：2011-07-12
申请号：US12059059
申请日：2008-03-31
申请人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
发明人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/28132 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.
摘要翻译： 诸如CMOS半导体结构的半导体结构包括具有不对称的多个源区和漏区的场效应器件。 通过使用包括与倾斜斜面区域相邻并相邻的水平平台区域的半导体衬底制造半导体结构来诱导这种源区和漏区不对称。 在CMOS半导体结构的上下文中，这种半导体衬底允许在不同的晶体取向半导体区域上制造pFET和nFET，而pFET和nFET（即，通常为pFET）中的一个具有不对称的源极和漏极区域 。
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5.发明申请ELECTRICAL FUSES COMPRISING THIN FILM TRANSISTORS (TFTS), AND METHODS FOR PROGRAMMING SAME 有权包含薄膜晶体管（TFTS）的电熔丝及其编程方法公开(公告)号：US20070158781A1
公开(公告)日：2007-07-12
申请号：US11306597
申请日：2006-01-04
IPC分类号： H01L29/00
CPC分类号： H01L29/42384 , H01L23/345 , H01L23/5256 , H01L29/78669 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated thin film transistor so as to cause at least partial dehydrogenation. Consequentially, the thin film transistor exhibits detectible physical property change(s), which defines a programmed state. In an alternative embodiment of the present invention, the electrical fuse comprises a thin film transistor that is either hydrogenated or not hydrogenated. Programming of such an alternative electrical fuse can be effectuated by applying a sufficient high back gate voltage to the thin film transistor to cause state changes in the channel-gate interface. In this manner, the thin film transistor also exhibits detectible property change(s) to define a programmed state.
摘要翻译： 本发明涉及电熔丝，每个电熔丝包括至少一个薄膜晶体管。 在一个实施例中，本发明的电熔丝包括具有相邻加热元件的氢化薄膜晶体管。 可以通过加热氢化薄膜晶体管来实现这种电熔丝的编程，从而至少部分脱氢。 因此，薄膜晶体管表现出可检测的物理特性变化，其定义了编程状态。 在本发明的替代实施例中，电熔丝包括被氢化或未氢化的薄膜晶体管。 可以通过向薄膜晶体管施加足够的高背栅电压来引起通道栅极界面的状态变化来实现这种替代电熔丝的编程。 以这种方式，薄膜晶体管还具有可检测的特性变化以限定编程状态。
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6.发明授权Orientation-optimized PFETS in CMOS devices employing dual stress liners 失效采用双重应力衬垫的CMOS器件中的取向优化PFETS公开(公告)号：US07525162B2
公开(公告)日：2009-04-28
申请号：US11850933
申请日：2007-09-06
申请人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
发明人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/7843
摘要： A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 1 0] crystallographic direction in the (110) silicon layer is from about 25° to about 55.
摘要翻译： 在具有（110）表面取向且位于衬底中的硅层上提供PFET。 设置在PFET的栅极和源极/漏极区域上的压应力衬垫沿着PFET沟道的方向产生初级纵向压缩应变。 设置在横向邻近PFET的至少一个NFET上的拉伸应力衬垫沿着NFET通道的方向产生初级纵向拉伸应变。 来自至少一个NFET拉伸衬套的二次应力场在PFET通道中产生有益的横向拉伸应力。 当PFET通道的方向与平面内[1
10]晶体方向的方位角之间时，主压缩纵向应变和次级拉伸横向应力的净效益最大化 （110）硅层为约25°至约55°。 -
7.发明申请ORIENTATION-OPTIMIZED PFETS IN CMOS DEVICES EMPLOYING DUAL STRESS LINERS 失效使用双应力衬片的CMOS器件中的方位优化PFET公开(公告)号：US20090065867A1
公开(公告)日：2009-03-12
申请号：US11850933
申请日：2007-09-06
申请人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
发明人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/7843
摘要： A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 10] crystallographic direction in the (110) silicon layer is from about 25° to about 55.
摘要翻译： 在具有（110）表面取向且位于衬底中的硅层上提供PFET。 设置在PFET的栅极和源极/漏极区域上的压应力衬垫沿着PFET沟道的方向产生初级纵向压缩应变。 设置在横向邻近PFET的至少一个NFET上的拉伸应力衬垫沿着NFET通道的方向产生初级纵向拉伸应变。 来自至少一个NFET拉伸衬套的二次应力场在PFET通道中产生有益的横向拉伸应力。 当PFET通道的方向和平面内[1
10]晶体方向的方位角在（（））时，主压缩纵向应变和次拉伸横向应力的最大优点是最大化， 110）硅层为约25°至约55°。 -
8.发明授权Structure and method for thermally stressing or testing a semiconductor device 有权用于热应力或测试半导体器件的结构和方法公开(公告)号：US07375371B2
公开(公告)日：2008-05-20
申请号：US11307324
申请日：2006-02-01
CPC分类号： G01R31/2856
摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.
摘要翻译： 提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。 一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。 通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。 分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。
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公开(公告)号：US08089160B2
公开(公告)日：2012-01-03
申请号：US11954866
申请日：2007-12-12
申请人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
发明人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect according to one embodiment includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to a top portion of the first via; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at a bottom end and to a metal power line at a top end thereof, wherein the first via is coupled to a first end of the buffer metal segment and the plurality of second vias are coupled to a second end of the buffer metal segment, such that the first via is horizontally off-set from all of the plurality of second vias, wherein the butter metal segment is substantially shorter in length than the metal power line.
摘要翻译： 根据一个实施例的IC互连包括位于电介质中并且在一端耦合到高电流器件的第一通孔; 位于电介质中并耦合到第一通孔的顶部的缓冲金属段; 以及多个第二通孔，其位于电介质中并在底端处连接到缓冲金属段，并在其顶端处连接到金属电源线，其中第一通孔耦合到缓冲金属段的第一端，并且 多个第二通孔耦合到缓冲金属段的第二端，使得第一通孔与所有多个第二通孔水平偏移，其中黄金金属段的长度短于金属电源线 。
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公开(公告)号：US20090152724A1
公开(公告)日：2009-06-18
申请号：US11954866
申请日：2007-12-12
申请人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
发明人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first via at the other end thereof; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at one end and to a metal power line at the other end thereof, wherein the buffer metal segment is substantially shorter in length than the metal power line.
摘要翻译： 公开了用于大电流器件的IC互连，其设计结构和方法。 IC互连的一个实施例包括位于电介质中的第一通孔，并在一端连接到高电流装置; 位于电介质中并在其另一端耦合到第一通孔的缓冲金属段; 以及多个第二通孔，其位于电介质中并且在一端处连接到缓冲金属段，并且在另一端处连接到金属电源线，其中所述缓冲金属段的长度短于金属电源线。
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